ZHCSCD9C April   2014  – August 2014 ADC16DX370

PRODUCTION DATA.  

1. 1 特性
2. 2 应用范围
3. 3 说明
4. 4 修订历史记录
5. 5 Pin Configuration and Functions
6. 6 Specifications
   1. 6.1  Absolute Maximum Ratings
   2. 6.2  Handling Ratings
   3. 6.3  Recommended Operating Conditions
   4. 6.4  Thermal Information
   5. 6.5  Converter Performance Characteristics
   6. 6.6  Power Supply Electrical Characteristics
   7. 6.7  Analog Interface Electrical Characteristics
   8. 6.8  CLKIN, SYSREF, SYNCb Interface Electrical Characteristics
   9. 6.9  Serial Data Output Interface Electrical Characteristics
   10. 6.10 Digital Input Electrical Interface Characteristics
   11. 6.11 Timing Requirements
   12. 6.12 Typical Characteristics
7. 7 Parameter Measurement Information
   1. 7.1 Over-Range Functional Characteristics
   2. 7.2 Input Clock Divider and Clock Phase Adjustment Functional Characteristics
   3. 7.3 JESD204B Interface Functional Characteristics
8. 8 Detailed Description
   1. 8.1 Overview
   2. 8.2 Functional Block Diagram
   3. 8.3 Feature Description
      1. 8.3.1  Amplitude and Phase Imbalance Correction of Differential Analog Input
      2. 8.3.2  DC Offset Correction
      3. 8.3.3  Over-Range Detection
      4. 8.3.4  Input Clock Divider
      5. 8.3.5  SYSREF Offset Feature and Detection Gate
      6. 8.3.6  Sampling Instant Phase Adjustment
      7. 8.3.7  Serial Differential Output Drivers
         1. 8.3.7.1 De-Emphasis Equalization
      8. 8.3.8  ADC Core Calibration
      9. 8.3.9  Data Format
      10. 8.3.10 JESD204B Supported Features
      11. 8.3.11 Transport Layer Configuration
          1. 8.3.11.1 Lane Configuration
          2. 8.3.11.2 Frame Format
          3. 8.3.11.3 ILA Information
      12. 8.3.12 Test Pattern Sequences
      13. 8.3.13 JESD204B Link Initialization
      14. 8.3.14 SPI
   4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down and Sleep Modes
   5. 8.5 Register Map
      1. 8.5.1 Register Descriptions
9. 9 Application and Implementation
   1. 9.1 Application Information
      1. 9.1.1 Analog Input Considerations
         1. 9.1.1.1 Differential Analog Inputs and Full Scale Range
         2. 9.1.1.2 Analog Input Network Model
         3. 9.1.1.3 Input Bandwidth
         4. 9.1.1.4 Driving the Analog Input
         5. 9.1.1.5 Clipping and Over-Range
      2. 9.1.2 CLKIN, SYSREF, and SYNCb Input Considerations
         1. 9.1.2.1 Driving the CLKIN+ and CLKIN- Input
         2. 9.1.2.2 Clock Noise and Edge Rate
         3. 9.1.2.3 Driving the SYSREF Input
         4. 9.1.2.4 SYSREF Signaling
         5. 9.1.2.5 SYSREF Timing
         6. 9.1.2.6 Effectively Using the SYSREF Offset and Detection Gate Features
         7. 9.1.2.7 Driving the SYNCb Input
      3. 9.1.3 Output Serial Interface Considerations
         1. 9.1.3.1 Output Serial-Lane Interface
         2. 9.1.3.2 Voltage Swing and De-Emphasis Optimization
         3. 9.1.3.3 Minimizing EMI
      4. 9.1.4 JESD204B System Considerations
         1. 9.1.4.1 Frame and LMFC Clock Alignment Procedure
         2. 9.1.4.2 Link Interruption
         3. 9.1.4.3 Synchronization Requests and SYNCb Alignment in Multi-Device Systems
         4. 9.1.4.4 Clock Configuration Examples
         5. 9.1.4.5 Configuring the JESD204B Receiver
      5. 9.1.5 SPI
   2. 9.2 Typical Application
      1. 9.2.1 High-IF Sampling Receiver
         1. 9.2.1.1 Design Requirements
         2. 9.2.1.2 Design Procedure
         3. 9.2.1.3 Application Curve
10. 10Power Supply Recommendations
    1. 10.1 Power Supply Design
    2. 10.2 Decoupling
11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
12. 12器件和文档支持
    1. 12.1 器件支持
       1. 12.1.1 技术规格定义
       2. 12.1.2 JESD204B 定义
    2. 12.2 商标
    3. 12.3 静电放电警告
    4. 12.4 Glossary
13. 13机械、封装和可订购信息