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ZHCSE48B September 2015 – January 2019 ADC31JB68

PRODUCTION DATA.

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RTA|40
- MPQF134A

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RTA|40
- QFND447B

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6.7 Electrical Characteristics: Interface

typical values at T_A = 25°C, full temperature range is T_MIN = –40°C to T_MAX = 85°C, ADC sampling rate = 500 MSPS, 50% clock duty cycle, VA3.0 = 3 V; VA1.8 = 1.8 V; VA1.2 = VACLK1.2 = 1.2 V; –1 dBFS differential input, and R_(term) = 100 Ω (unless otherwise noted) (see the Interface Circuits section)

PARAMETER		NOTES	MIN	TYP	MAX	UNIT
ANALOG INPUTS (VIN+, VIN-)
V_(FSR)	Full-scale range voltage	Differential peak-to-peak		1.7		V
V_CM	Nominal input common-mode voltage			1.6		V
ΔV_CM	Maximum input common mode voltage range			V_CM ± 0.05		V
R_IN	Input termination resistance	Differential resistance at dc		190		Ω
C_IN	Input capacitance	Differential		4.6		pF
INPUT COMMON MODE REFERENCE (VCM)
V_(VCM)	Common-mode reference voltage output			1.6		V
I_(VCM)	Maximum VCM pin current load			1		mA
CLOCK INPUT (CLKIN+, CLKIN-)
V_ID-MAX	Maximum input voltage swing⁽¹⁾	Differential peak voltage			1000	mV
V_ID-MIN	Minimum input voltage swing⁽¹⁾	Differential peak voltage		250		mV
dV_SS/dt	Input edge rate at zero crossing⁽¹⁾	Recommended minimum		5		V/ns
V_(IS-BIAS)	Input common-mode internal bias voltage⁽²⁾⁽¹⁾			0.5		V
V_(IS-IN)	Externally applied common-mode voltage⁽¹⁾	DC-coupled interface		0.5 ± 0.1		V
Z_(rdiff)	Input termination resistance⁽²⁾	Differential resistance at dc		100		Ω
Z_tt	Common-mode internal bias source impedance⁽²⁾			10		kΩ
C_T	Input capacitance⁽²⁾	Differential		2		pF
SYSREF INPUT (SYSREF+, SYSREF-)
V_ID-MAX	Maximum input voltage swing⁽¹⁾	Differential peak voltage			1000	mV
V_ID-MIN	Minimum input voltage swing⁽¹⁾	Differential peak voltage		250		mV
V_(IS-BIAS)	Input common-mode internal bias voltage⁽¹⁾			0.5		V
V_(IS-IN)	Externally applied common mode voltage⁽¹⁾	DC-coupled interface, typical value depends on the configuration of the SYS_CM parameter				V
		SYS_CM = 00		0.5 ± 0.1
		SYS_CM = 01		0.8 ± 0.2
		SYS_CM = 10		1.25 ± 0.25
		SYS_CM = 11		1.75 ± 0.25
Z_(rdiff)	Input termination resistance⁽²⁾	Differential resistance at dc		100		Ω
Ztt	Common-mode internal bias source impedance⁽²⁾			14		kΩ
C_T	Input capacitance⁽²⁾	Differential		1		pF
SYNCb INPUT (SYNCb+, SYNCb-)
V_ID	Input voltage swing⁽¹⁾	Differential peak voltage		350		mV
V_(IS-IN)	Externally applied common-mode voltage⁽¹⁾	DC-coupled interface		1.25 ± 0.75		V
Z_(rdiff)	Input termination resistance⁽²⁾	Differential resistance at dc		100		Ω
C_T	Input capacitance⁽²⁾	Differential		1		pF
SERDES OUTPUT (SO0+/-, SO1+/-) Meets JESD204B LV-OIF-11G-SR Standard
V_OD	Output differential voltage⁽³⁾	Differential peak-peak voltage, de-emphasis disabled (DEM = 0)				mV
		VOD = 0		400
		VOD = 1		470
		VOD = 2		540
		VOD = 3		610
		VOD = 4		670
		VOD = 5		740
		VOD = 6		790
		VOD = 7		840
R_(deepm)	Transmitter de-emphasis range	Configurable via SPI, VOD configured to 4				dB
		DEM=0		0.0
		DEM=1		–0.8
		DEM=2		–2.4
		DEM=3		–3.8
		DEM=4		–4.9
		DEM=5		–6.3
		DEM=6		–7.7
		DEM=7		–10.3
I_SC	Transmitter short circuit current	Transmitter terminals shorted to each other or ground, power on		23		mA
Z_(ddiff)	Differential output impedance⁽⁴⁾			100		Ω
R_L(ddiff)	Differential output return loss magnitude	Relative to 100 Ω, for frequencies from 100 MHz to 0.75 × baud rate; default VOD and DEM.		–8.5		dB
SCLK, SDI, CSB INPUT
V_IH	Logical 1 input voltage	Inputs are compatible with 1.2-V up to 3-V logic.	0.9			V
V_IL	Logical 0 input voltage				0.3	V
I_IN0	Logic low input current			4		nA
I_IN1	Logic high input current			–8		nA
C_IN	Input capacitance			2		pF
SDO/OVR OUTPUT
V_OH	Logical 1 output voltage⁽⁵⁾	V_SPI = 1.2 V, 1.8 V, or 3 V, configurable via SPI	V_SPI – 0.2	V_SPI⁽⁵⁾		V
V_OL	Logical 0 output voltage⁽⁵⁾			0	0.3	V
+I_SC	Logic high short circuit current	V_SPI = 1.8 V		9		mA
–I_SC	Logic low short circuit current	V_SPI = 1.8 V		–14		mA

(1) Specification applies to the electrical level diagram of Figure 26

(2) Specification applies to the electrical circuit diagram of Figure 27

(3) Specification applies to the electrical level diagram of Figure 28

(4) Specification applies to the electrical circuit diagram of Figure 29

(5) The SPI_CFG register must be changed to a supported output logic level after power up and before a SPI read command is executed. Until that time, the output voltage on SDO/OVR may be as high as the VA3.0 supply during a SPI read command. The SDO/OVR output is high-Z at all times except during a read command.