8.1 Overview

The ADC31JB68 is a low-power, wide-bandwidth, 16-bit, 500-MSPS analog-to-digital converter (ADC). The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. This device is designed for sampling analog input signals of up to 1300 MHz.

The ADC31JB68 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. On-chip dither provides an exceptionally clean noise floor. Embedded foreground and background calibration ensures consistent dynamic performance over the entire temperature range and minimizes part-to-part variation.

The device outputs its digital data from a JESD204B serial interface with two lanes transferring data at up to 5 Gbps/lane. The interface significantly reduces the number of lanes compared to an LVDS interface, allowing high system integration density. An internal phase locked loop (PLL) transparently generates the necessary clocking for data serialization.

The ADC31JB68 is offered in a 40- pin QFN (6 x 6mm) package and supports the full industrial temperature range.