8.3.3 Over-Range Detection

Over-range detection is available via the shared SDO/OVR dual-mode pin. Configuration of the SDO/OVR pin into the over-range mode is done through the SPI. By default, the over-range mode is not selected. The SDO/OVR pin asserts (logical high) when an over-range signal is detected at the input. The short delay from when an over-range signal is incident at the input until the SDO/OVR output is asserted allows for almost immediate detection of over-range signals without delay from the internal ADC pipeline latency or serial link latency.

The input power threshold to indicate an over-range event is programmable via the SPI in steps of 128 codes relative to the 16-bit code range of the data at the output of the ADC core.

After an over-range event occurs and the signal at the channel input reduces to a level below full-scale, an internal counter begins counting to provide a hold function. When the counter reaches the hold counter threshold, the over-range signal is de-asserted (logical low). The duration of the hold counter is programmable via the SPI to hold for +3, +7, or +15 frame clock cycles. The counter is disabled (+0 cycles) by default to allow de-assertion without holding.