8.3.4 Input Clock Divider

An input clock divider allows a high frequency clock signal to be distributed throughout the system and locally divided down at the ADC device. The frequency at the CLKIN input may be divided down to the sampling rate of the ADC by factors of 1, 2, or 4. Changing the clock divider setting initiates a JESD204 link re-initialization and requires re-calibration of the ADC if the sampling rate is changed from the rate during the previous calibration (see ADC Core Calibration).