8.3.5 SYSREF Detection Gate

When the signal at the SYSREF input is not actively toggling periodically, the SYSREF signal is considered to be in an idle state. The idle state is recommended at any time the ADC31JB68 spurious performance must be maximized. The SYSREF detection gate is provided to prevent transitions of the SYSREF signal in and out of the idle state from impacting the JESD204B core. While the SYSREF signal is In the idle state, the SYSREF detection gate should be used reject noise that may appear on the SYSREF signal.

The detection gate is the AND gate shown in Figure 72. The gate enables or disables propagation of the SYSREF signal through to the internal device logic. If the detection gate is disabled and a false edge appears at the SYSREF input, the signal does not disrupt the internal clock alignment. Note that the SYSREF detection gate is disabled by default; therefore, the device does not respond to a SYSREF edge until the detection gate is enabled.

The SYSREF detection gate features is controlled through the SPI.