ZHCSE48B September 2015 – January 2019 ADC31JB68
PRODUCTION DATA.
Table 3 summarizes the information transmitted during the initial lane alignment (ILA) sequence. Mapping of these parameters into the data stream is described in the JESD204B standard.
| Parameter | Description | Logical Value | Encoded Value |
|---|---|---|---|
| ADJCNT | DAC LMFC adjustment | 0 | 0 |
| ADJDIR | DAC LMFC adjustment direction | 0 | 0 |
| BID | Bank ID | 0 | 0 |
| CF | Number of control words per frame clock period per link | 0 | 0 |
| CS | Number of control bits per sample | 0 | 0 |
| DID | Device identification number | 0 | 0 |
| F | Number of octets per frame (per lane)(1) | 1 | 0 |
| HD | High-density format | 1 | 1 |
| JESDV | JESD204 version | 1 | 1 |
| K | Number of frames per multi-frame(1) | Set by register
as 17 to 32 |
16 to 31 |
| L | Number of lanes per link(1) | 2 | 1 |
| LID | Lane identification number | 0 (lane 0), 1 (lane 1) | 0 or 1 |
| M | Number of converters per device(1) | 1 | 0 |
| N | Converter resolution (1) | 16 | 15 |
| N’ | Total number of bits per sample(1) | 16 | 15 |
| PHADJ | Phase adjustment request to DAC | 0 | 0 |
| S | Number of samples per converter per frame cycle(1) | 1 | 0 |
| SCR | Scrambling enabled | Set by register
as 0 (disabled) or 1 |
0 or 1 |
| SUBCLASSV | Device subclass version | 1 | 1 |
| RES1 | Reserved field 1 | 0 | 0 |
| RES2 | Reserved field 2 | 0 | 0 |
| FCHK | Checksum(2) | Computed | Computed |
Scrambling of the output serial data is supported and conforms to the JESD204B standard. Scrambling is disabled by default, but may be enabled via the SPI. When scrambling is enabled, the ADC31JB68 device supports the early synchronization option by the receiver during the ILA sequence, although the ILA sequence data is never scrambled.