8.3.13.1 Frame Alignment

The Frame Alignment step requires alignment of the frame and local multi-frame clocks within the ADC31JB68 device to an external reference. This is accomplished by providing the device clock and SYSREF clock to the CLKIN and SYSREF inputs, respectively. The ADC31JB68 device aligns its frame clock and LMFC to any SYSREF rising edge event, offset by a SYSREF-to-LMFC propagation delay.

The SYSREF signal must be source synchronous to the device clock; therefore, the SYSREF rising edge must meet setup and hold requirements relative to the signal at the CLKIN input. If these requirements cannot be met, then the alignment of the internal frame and multi-frame clocks cannot be specified. As a result, a link may still be established, but the latency through the link cannot be deterministic. Frame alignment may occur at any time but a re-alignment of the internal frame clock and LMFC will break the link. Note that frame alignment is not required for the ADC31JB68 device to establish a link because the device automatically generates the clocks on power-up with unknown phase alignment.