ZHCSE48B September 2015 – January 2019 ADC31JB68
PRODUCTION DATA.
The ADC31JB68 is packaged in a 40-pin QFN package (6 x 6 x 0.8, 0.5 mm pin-pitch) with a bottom-side exposed paddle.
PIN | TYPE or DIAGRAM | DESCRIPTION | ||||
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NAME | NO. | |||||
INPUT/REFERENCE | ||||||
VIN+
VIN– |
4, 5 |
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Differential analog input pins.
The differential full-scale signal level is 1.7 Vpp. Each input pin is terminated to the internal 1.6V common-mode reference with a 100 Ω resistor for a 200 Ω total differential termination. |
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VCM | 7 | Input Interface Common mode voltage.
This pin must be bypassed to AGND with a low ESL (equivalent series inductance) 0.1 µF capacitor that is placed as close to the pin as possible to minimize stray inductance. A 10 µF capacitor should also be placed in parallel. It is recommended to use VCM to provide the common mode voltage for the differential analog inputs. The input common-mode bias is provided internally for the ADC input, therefore external use of VCM is recommended but not strictly required. The recommended decoupling is always required. |
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CLOCK/SYNC | ||||||
CLKIN+
CLKIN– |
11, 12 |
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Differential device clock input pins.
AC coupling is recommended for coupling the clock input to these pins. DC biasing of the clock receiver is provided internally. Each pin is internally terminated to the 500mV DC bias with 50 Ω resistor for a 100 Ω total internal differential termination resistor. Sampling occurs on the falling edge of the differential signal (CLKIN+) − (CLKIN-). |
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SYSREF+,
SYSREF– |
17, 18 | Differential SYSREF signal input pins.
Each pin is internally terminated to the DC bias with a large resistor. An internal 100 Ω differential termination is provided therefore an external termination is not required. Additional resistive components in the input structure give the SYSREF input a wide input common mode range. |
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SYNCb+
SYNCb– |
19, 20 | Differential SYNCb signal input pins. | ||||
DC coupling is required for coupling the SYNCb signal to these pins. Each pin is internally terminated to the DC bias with a large resistor. An internal 100 Ω differential termination is provided therefore an external termination is not required. Additional resistive components in the input structure give the SYNCb input a wide input common mode range. The SYNCb signal is active low and is therefore asserted when the voltage at SYNCb+ is less than at SYNCb–. | ||||||
SERIAL INTERFACE (SPI) | ||||||
SCLK | 32 | SPI Interface Serial Clock pin.
Serial data is shifted into and out of the device synchronous with this clock signal. Compatible with 1.2–3.0V CMOS logic levels. |
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CSB | 31 | SPI Interface Chip Select pin.
When this signal is asserted, SCLK is used to clock input serial data on the SDI pin or output serial data on the SDO pin. When this signal is de-asserted, the SDO pin is high impedance and the input data is ignored. Active low. A 1kΩ pull-up resistor to the VA1.8 supply is recommended to prevent undesired activation of the SPI bus. Compatible with 1.2–3.0V CMOS logic levels. |
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SDI | 33 | SPI Interface Data Input pin.
Serial data is shifted into the device on this pin while the CSB signal is asserted. Compatible with 1.2-3.0V CMOS logic levels. |
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SDO/OVR | 34 | SPI Data Output and Over-Range pin.
Dual mode pin. When configured as SDO, serial data of the SPI is shifted out of the device on this pin while CSB is asserted. When configured as OVR, the over-range signal is output. Pin mode configurable via the SPI. Output voltage is configurable to 1.2V, 1.8V, or 3.0V CMOS logic levels via the SPI. Default configuration outputs the SDO at a 1.8V logic level. |
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DIGITAL OUTPUT INTERFACE | ||||||
SO0+, SO0–,
SO1+, SO1– |
25, 26,
23, 24 |
Differential High Speed Serial Data Lane pins.
These pins must be AC coupled to the receiving device. The differential trace routing from these pins must maintain a 100 Ω characteristic impedance. |
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POWER SUPPLY | ||||||
VA3.0 | 1, 2 | Supply Input Pin | 3 V Analog Power Supply pin. | |||
This pin must be connected to a quiet source and decoupled to AGND with a 0.1 µF capacitor located close to each pin and a second 0.1 µF capacitor on bottom layer. | ||||||
VA1.8 | 15, 16, 28, 39, 40 | Supply Input Pin | 1.8 V Analog Power Supply pins. | |||
These pins must be connected to a quiet source and decoupled to AGND with a
0.1 µF capacitor located close to each pin and a second 0.1 µF capacitor on bottom layer. |
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VA1.2 | 21, 29, 35, 36 | Supply Input Pin | 1.2 V Analog Power Supply pins. | |||
These pins must be connected to a quiet source and decoupled to AGND with a 0.1 µF capacitor located close to each pin and a second 0.1 µF capacitor on bottom layer. | ||||||
VACLK1.2 | 8, 9 | Supply Input Pin | 1.2 V Analog Power Supply pins for internal clock path. | |||
These pins must be connected to a quiet source and decoupled to AGND with a 0.1 µF capacitor located close to each pin and a second 0.1 µF capacitor on bottom layer. | ||||||
AGND | 3, 6, 10, 13, 14, 22, 27, 30, 37, 38 | Analog Ground | Analog Ground. | |||
Solid ground reference planes under the device are recommended. | ||||||
Exposed Thermal Pad | Exposed Thermal Pad. | |||||
The exposed pad must be connected to the AGND ground plane electrically and with good thermal dissipation properties to ensure rated performance. |