ZHCSE48B September 2015 – January 2019 ADC31JB68
PRODUCTION DATA.
The signal to noise ratio of the ADC is limited by the following noise sources inherent to the device: 1) Quantization Noise, 2) Thermal Noise, 3) Sampling Instant Noise (Aperture Jitter). These sources combine together to limit the noise performance of the converter as described by Equation 1. Noise sources external to the ADC can generally be included in this equation as an RMS summation to determine system performance.
Quantization noise is independent of the input signal but does not affect the noise performance of the ADC31JB68 because the SNR limitation of a 16-bit ADC due to quantization noise is 96-dB, well above the SNR of this device. The thermal noise is input independent, spread evenly across the spectrum, and the main limitation for signals with lower frequencies or lower amplitudes.
If quantization and thermal noise is ignored, the fundamental SNR limitation due to aperture jitter can be calculated using Equation 2.
Signals with larger amplitudes and higher frequencies introduce signal dependent sampling instant noise due to the Jitter on the sampling clock edge. This noise includes a broadband component that raises the overall noise spectral density as well as a in-close noise component that is spectrally shaped and concentrates around the signal in the spectrum. The differential clock receiver of the ADC31JB68 has a very-low noise floor and wide bandwidth. Minimizing the aperture jitter requires a sampling clock with a steep edge rate at the zero crossing. Lesser edge rates increase the aperture jitter as demonstrated in Figure 58 which shows the SNR limitation due to aperture jitter as a function of clock edge range and input signal frequency.