9.1.1.2 External Noise Sources

Noise sources external to the ADC device that impact the overall system performance through the ADC include: 1) Analog Input Signal Path noise, 2) Sampling Clock Signal Path Noise, 3) Supply Noise

Analog input signal path noise comes from devices in the signal path prior to the ADC and enters through the analog input (VIN+/-). An anti-aliasing filter must be included in front of the ADC to limit the noise bandwidth and prevent the aliasing of noise into any band of interest. Sampling clock signal path noise enters through the sampling clock input (CLKIN+/-) and adds noise similar to the Aperture Jitter. External clock jitter can be minimized by using high quality clock sources and jitter cleaners (PLLs) as well as bandpass filters at the clock input.

The total clock jitter (T_Jitter), including the aperture jitter of the ADC and external clock noise can be calculated with Equation 3 and applied to Equation 1 and Equation 2 to determine the system impact. Figure 59 shows the simulated impact on the SNR of the ADC31JB68 output spectrum for a given total jitter and input signal frequency.

Equation 3.

Figure 59. SNR Limit Due to Total Jitter of Sampling Clock With a -1 dBFS Input Signal

Additional noise may couple to the clock path through power supplies. Take care to provide a very-low noise power supply and isolated supply return path to minimize noise added to the supply. Spurious noise added to the clock path results in symmetrical, modulated spurs around large input signals. These spurs have a constant magnitude in units of dB relative to the input signal amplitude or carrier, [dBc].