9.1.3 CLKIN, SYSREF, and SYNCb Input Considerations

Clocking the ADC31JB68 device shares many common concepts and system design requirements with previously released ADC products that include a JESD204B interface. A SYSREF signal accompanies the device clock to provide phase alignment information for the output data serializer (as well as for the sampling instant when the clock divider is enabled) to ensure that the latency through the JESD204B link is always deterministic, a concept called deterministic latency. To ensure deterministic latency, the SYSREF signal must meet setup and hold requirements relative to CLKIN and the design of the clocking interfaces require close attention. As with other ADCs, the quality of the clock signal also influences the noise and spurious performance of the device.