9.1.3.1 Driving the CLKIN+ and CLKIN– Input

The CLKIN input circuit is composed of a differential receiver and an internal 100-Ω termination to a weakly driven common-mode of 0.5 V. TI recommends AC coupling to the CLKIN input with 0.1-uF external capacitors to maintain the optimal common-mode biasing. Figure 70 shows the CLKIN receiver circuit and an example AC coupled interface.

Figure 70. Driving the CLKIN Input With an AC Coupled Interface

DC coupling is allowed as long as the input common-mode range requirements are satisfied. The input common-mode of the CLKIN input is not compatible with many common signaling standards like LVDS and LVPECL. Therefore, the CLKIN signal driver common-mode must be customized at the transmitter or adjusted along the interface. Figure 71 shows an example DC coupled interface that uses a resistor divider network to reduce the common-mode while maintaining a 100-Ω total termination at the load. Design equations are provided with example values to determine the resistor values.

Figure 71. Driving the CLKIN Input With an Example DC Coupled Interface

The CLKIN input supports any type of standard signaling that meets the input signal swing and common-mode range requirements with an appropriate interface. Generic differential sinusoidal or square-wave clock signals are also supported. TI does not recommend driving the CLKIN input single-ended. The differential lane trace on the PCB should be designed to be a controlled 100 Ω and protected from noise sources or other interfering signals.