9.1.3.2 Driving the SYSREF Input

The SYSREF input interface circuit is composed of the differential receiver, internal termination, internal common-mode bias with common-mode control, and SYSREF detection feature.

A 100-Ω differential termination is provided inside the ADC pins. A high impedance reference biases the input common-mode through a resistor network that can be configured to support a wide range of input common modes voltages. Following the receiver, an AND gate provides a method for detecting or ignoring incoming SYSREF events.

The timing relationship between the CLKIN and SYSREF signal is very stringent in a JESD204B system. Therefore, the signal path network of the CLKIN and SYSREF signals must be as similar as possible to ensure that the signal relationship is maintained from the launch of the signal, through their respective channels to the CLKIN and SYSREF input receivers.

DC coupling of the SYSREF signal to the input pins with the simple interface shown in Figure 72 is required. Although the input common-mode range of the receiver itself is limited, a wide input common-mode range is supported using the common-mode control feature which level-shifts the common-mode of the input signal to an appropriate level for the input receiver. The common-mode control feature is configured via the SPI.

Figure 72. SYSREF Input Receiver and DC Coupled Interface