9.1.3.5 Effectively Using the Detection Gate Feature

TI recommends the use of the SYSREF detection gate for most applications. The gate is enabled when SYSREF is being transmitted and the gate is disabled before the SYSREF transmitter is put in the idle state.

Enabling the SYSREF gate immediately sends a logic signal to a logic block responsible for aligning the internal frame clock and LMFC. If the signal at the SYSREF input is logic high when the gate is enabled, then a "false" rising edge event causes a re-alignment of the internal clocks, despite the fact that the event is not an actual SYSREF rising edge. The SYSREF rising edge following the gate enable then causes a subsequent re-alignment with the desired alignment.