9.1.5.1 Frame and LMFC Clock Alignment Procedure

Frame and LMFC clocks are generated inside the ADC31JB68 device and are used to properly align the phase of the serial data leaving the device. The phases of the frame and multi-frame clocks are determined by the frame alignment step for JESD204B link initialization as shown in Figure 35. These clocks are not accessible outside the device. The frequencies of the frame and LMFC must be equal to the frame and LMFC of the device receiving the serial data.

When the ADC31JB68 device is powered-up, the internal frame and local multi-frame clocks initially assume a default phase alignment. To ensure determinist latency through the JESD204B link, the frame and LMFC clocks of the ADC31JB68 device must be aligned in the system. Perform the following steps to align the device clocks:

1. Enable the SYSREF signal driver. See SYSREF Signaling for more information.
2. Enable detection of the SYSREF signal at the ADC31JB68 device by enabling the SYSREF detection gate. See Effectively Using the Detection Gate Feature for more information.
3. Apply the desired SYSREF signal at the ADC31JB68 device SYSREF input.
4. Disable detection of the SYSREF signal by disabling the SYSREF gate.
5. Configure the SYSREF driver into its idle state.