The ADC344x has a SYSREF input pin that can be used when the clock-divider feature is used. A logic low-to-high transition on the SYSREF pin aligns the falling edge of the divided clock with the next falling edge of the input clock, essentially resetting the phase of the divided clock, as shown in Figure 8-6. When multiple ADC344x devices are onboard and the clock divider option is used, the phase of the divided clock among the devices may not be the same. The phase of the divided clock in each device can be synchronized to the common sampling clock by using the SYSREF pins. SYSREF can applied as mono-shot or periodic waveform. When applied as periodic waveform, its period must be integer multiple of period of the divided clock. When not used, the SYSREFP and SYSREFM pins can be connected to AVDD and GND, respectively. Alternatively, the SYSREF buffer inside the device can be powered down using the PDN SYSREF register bit.

Figure 8-6 Using SYSREF for Synchronization