The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
0.95 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADC322x can be driven by the transformer-coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in Figure 8-1, Figure 8-2, and Figure 8-3. See Figure 8-4 for details regarding the internal clock buffer.

R_T = termination resistor, if necessary.

Figure 8-1 Differential Sine-Wave Clock Driving Circuit

Figure 8-2 LVDS Clock Driving Circuit

Figure 8-3 LVPECL Clock Driving Circuit

C_EQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.

Figure 8-4 Internal Clock Buffer

A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 8-5. However, for best performance the clock inputs must be driven differentially, thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input.

Figure 8-5 Single-Ended Clock Driving Circuit