10.1 Application Information

Typical applications involving transformer coupled circuits are discussed in this section. Transformers (such as ADT1-1WT or WBC1-1) can be used up to 250 MHz to achieve good phase and amplitude balances at ADC inputs. While designing the dc driving circuits, the ADC input impedance must be considered. Figure 176 and Figure 177 show the impedance (Z_in = R_in || C_in) across the ADC input pins.

Figure 176. Differential Input Resistance (R_IN)

Figure 177. Differential Input Capacitance (C_IN)

10.2 Typical Applications

10.2.1 Driving Circuit Design: Low Input Frequencies

Figure 178. Driving Circuit for Low Input Frequencies

10.2.1.1 Design Requirements

For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor in series with each input pin can be kept to damp out ringing caused by package parasitic. The drive circuit may have to be designed to minimize the impact of kick-back noise generated by sampling switches opening and closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and matched impedance to the source.

10.2.1.2 Detailed Design Procedure

A typical application involving using two back-to-back coupled transformers is shown in Figure 178. The circuit is optimized for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used with the series inductor (39 nH), this combination helps absorb the sampling glitches.

10.2.1.3 Application Curve

Figure 179 shows the performance obtained by using circuit shown in Figure 178.

SFDR = 102.6 dBc, SNR = 72.9 dBFS, SINAD = 72.8 dBFS, THD = 99.8 dBc, HD2 = –108.6 dBc, HD3 = –104.0 dBc

Figure 179. Performance FFT at 10 MHz (Low Input Frequency)

10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz

Figure 180. Driving Circuit for Mid-Range Input Frequencies (100 MHz < f_IN < 230 MHz)

10.2.2.1 Design Requirements

See the Design Requirements section for further details.

10.2.2.2 Detailed Design Procedure

When input frequencies are between 100 MHz to 230 MHz, an R-LC-R circuit can be used to optimize performance, as shown in Figure 180.

10.2.2.3 Application Curve

Figure 181 shows the performance obtained by using circuit shown in Figure 180.

SFDR = 96.4 dBc, SNR = 72.1 dBFS, SINAD = 72.0 dBFS, THD = 92.6 dBc, HD2 = –96.4 dBc, HD3 = –98.8 dBc

Figure 181. Performance FFT at 170 MHz (Mid Input Frequency)

10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz

Figure 182. Driving Circuit for High input Frequencies ( f_IN > 230 MHz)

10.2.3.1 Design Requirements

See the Design Requirements section for further details.

10.2.3.2 Detailed Design Procedure

For high input frequencies (> 230 MHz), using the R-C-R or R-LC-R circuit does not show significant improvement in performance. However, a series resistance of 10 Ω can be used as shown in Figure 182.

10.2.3.3 Application Curve

Figure 183 shows the performance obtained by using circuit shown in Figure 182.

SFDR = 76.2 dBc, SNR = 68.3 dBFS, SINAD = 67.5 dBFS, THD = 74.3 dBc, HD2 = –76.2 dBc, HD3 = –79.2 dBc

Figure 183. Performance FFT at 450 MHz (High Input Frequency)