ZHCSDY0A May   2014  – June 2015 ADC32J22 , ADC32J23 , ADC32J24 , ADC32J25

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: ADC32J22, ADC32J23
    7. 7.7  Electrical Characteristics: ADC32J24, ADC32J25
    8. 7.8  AC Performance: ADC32J25
    9. 7.9  AC Performance: ADC32J24
    10. 7.10 AC Performance: ADC32J23
    11. 7.11 AC Performance: ADC32J22
    12. 7.12 Digital Characteristics
    13. 7.13 Timing Requirements
    14. 7.14 Typical Characteristics: ADC32J25
    15. 7.15 Typical Characteristics: ADC32J24
    16. 7.16 Typical Characteristics: ADC32J23
    17. 7.17 Typical Characteristics: ADC32J22
    18. 7.18 Typical Characteristics: Common Plots
    19. 7.19 Typical Characteristics: Contour Plots
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Inputs
      2. 9.3.2 Clock Input
        1. 9.3.2.1 SNR and Clock Jitter
        2. 9.3.2.2 Input Clock Divider
      3. 9.3.3 Power-Down Control
      4. 9.3.4 Internal Dither Algorithm
      5. 9.3.5 JESD204B Interface
        1. 9.3.5.1 JESD204B Initial Lane Alignment (ILA)
        2. 9.3.5.2 JESD204B Test Patterns
        3. 9.3.5.3 JESD204B Frame Assembly
        4. 9.3.5.4 Digital Outputs
    4. 9.4 Device Functional Modes
      1. 9.4.1 Digital Gain
      2. 9.4.2 Overrange Indication
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
          1. 9.5.1.1.1 Serial Register Write
          2. 9.5.1.1.2 Serial Register Readout
      2. 9.5.2 Register Initialization
      3. 9.5.3 Start-Up Sequence
    6. 9.6 Register Maps
      1. 9.6.1 Summary of Special Mode Registers
      2. 9.6.2 Serial Register Descriptions
        1. 9.6.2.1  Register 01h (address = 01h)
        2. 9.6.2.2  Register 03h (address = 03h)
        3. 9.6.2.3  Register 04h (address = 04h)
        4. 9.6.2.4  Register 06h (address = 06h)
        5. 9.6.2.5  Register 07h (address = 07h)
        6. 9.6.2.6  Register 08h (address = 08h)
        7. 9.6.2.7  Register 09h (address = 09h)
        8. 9.6.2.8  Register 0Ah (address = 0Ah)
        9. 9.6.2.9  Register 0Bh (address = 0Bh)
        10. 9.6.2.10 Register 0Ch (address = 0Ch)
        11. 9.6.2.11 Register 0Dh (address = 0Dh)
        12. 9.6.2.12 Register 0Eh (address = 0Eh)
        13. 9.6.2.13 Register 0Fh (address = 0Fh)
        14. 9.6.2.14 Register 13h (address = 13h)
        15. 9.6.2.15 Register 15h (address = 15h)
        16. 9.6.2.16 Register 27h (address = 27h)
        17. 9.6.2.17 Register 2Ah (address = 2Ah)
        18. 9.6.2.18 Register 2Bh (address = 2Bh)
        19. 9.6.2.19 Register 2Fh (address = 2Fh)
        20. 9.6.2.20 Register 30h (address = 30h)
        21. 9.6.2.21 Register 31h (address = 31h)
        22. 9.6.2.22 Register 34h (address = 34h)
        23. 9.6.2.23 Register 3Ah (address = 3Ah)
        24. 9.6.2.24 Register 3Bh (address = 3Bh)
        25. 9.6.2.25 Register 3Ch (address = 3Ch)
        26. 9.6.2.26 Register 422h (address = 422h)
        27. 9.6.2.27 Register 434h (address = 434h)
        28. 9.6.2.28 Register 522h (address = 522h)
        29. 9.6.2.29 Register 534 (address = 534h)
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Driving Circuit Design: Low Input Frequencies
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 相关链接
    2. 13.2 社区资源
    3. 13.3 商标
    4. 13.4 静电放电警告
    5. 13.5 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage range, AVDD –0.3 2.1 V
Supply voltage range, DVDD –0.3 2.1 V
Voltage applied to input pins: INAP, INBP –0.3 AVDD + 0.3 V
CLKP, CLKM –0.3 AVDD + 0.3 V
SYSREFP, SYSREFM, SYNCP~, SYNCM~ –0.3 AVDD + 0.3 V
SCLK, SEN, SDATA, RESET, PDN –0.3 AVDD + 0.3 V
Temperature range Operating free-air, TA –40 85 °C
Operating junction, TJ 125 °C
Storage, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
SUPPLIES
AVDD Analog supply voltage range 1.7 1.8 1.9 V
DVDD Digital supply voltage range 1.7 1.8 1.9 V
ANALOG INPUT
VID Differential input voltage For input frequencies < 450 MHz 2 VPP
For input frequencies < 600 MHz 1 VPP
VIC Input common-mode voltage VCM ± 0.025 V
CLOCK INPUT
Input clock frequency Sampling clock frequency 25 160(1) MSPS
Input clock amplitude (differential) Sine wave, ac-coupled 1.5 V
LPECL, ac-coupled 1.6 V
LVDS, ac-coupled 0.7 V
Input clock duty cycle 50%
Input clock common-mode voltage 0.95 V
DIGITAL OUTPUTS
CLOAD Maximum external load capacitance from each output pin to GND 3.3 pF
RLOAD Single-ended load resistance 100 Ω
(1) With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 640 MSPS.

7.4 Thermal Information

THERMAL METRIC(1) ADC32J2x UNIT
RGZ (VQFN)
48 PINS
RθJA Junction-to-ambient thermal resistance 25.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 18.9 °C/W
RθJB Junction-to-board thermal resistance 3.0 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Differential input full-scale 2.0 VPP
Input resistance Differential at dc 6.5 kΩ
Input capacitance Differential at dc 5.2 pF
VCM common-mode voltage output 0.95 V
VCM output current capability 10 mA
Input common-mode current Per analog input pin 1.5 µA/MSPS
Analog input bandwidth (3 dB) 50-Ω differential source driving 50-Ω termination across INP and INM 450 MHz
DC ACCURACY
Offset error –20 20 mV
EG(REF) Gain error as a result of internal reference inaccuracy alone –3 3 %FS
EG(CHAN) Gain error of channel alone ±1 %FS
Temperature coefficient of EG(CHAN) –0.017 Δ%FS/°C
CHANNEL-TO-CHANNEL ISOLATION
Crosstalk fIN = 10 MHz 105 dB
fIN = 100 MHz 105 dB
fIN = 200 MHz 105 dB
fIN = 230 MHz 105 dB
fIN = 300 MHz 105 dB

7.6 Electrical Characteristics: ADC32J22, ADC32J23

Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER ADC32J22 ADC32J23 UNIT
MIN TYP MAX MIN TYP MAX
ADC clock frequency 50 80 MSPS
Resolution 12 12 Bits
1.8-V analog supply current 134 267 152 272 mA
1.8-V digital supply current 22 40 31 46 mA
Total power dissipation 281 435 329 450 mW
Global power-down dissipation 5 5 mW
Wake-up time from global power-down 85 85 µs
Standby power-down dissipation 99 105 mW
Wake-up time from standby power-down 35 35 µs

7.7 Electrical Characteristics: ADC32J24, ADC32J25

Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER ADC32J24 ADC32J25 UNIT
MIN TYP MAX MIN TYP MAX
ADC clock frequency 125 160 MSPS
Resolution 12 12 Bits
1.8-V analog supply current 177 292 192 302 mA
1.8-V digital supply current 46 65 56 80 mA
Total power dissipation 401 535 454 560 mW
Global power-down dissipation 5 5 mW
Wake-up time from global power-down 85 85 µs
Standby power-down dissipation 112 118 mW
Wake-up time from standby power-down 35 35 µs

7.8 AC Performance: ADC32J25

Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS ADC32J25 (fS = 160 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
DYNAMIC AC CHARACTERISTICS
SNR Signal-to-noise ratio fIN = 10 MHz 70.3 70.5 dBFS
fIN = 70 MHz 68 69.8 70.0
fIN = 100 MHz 69.5 69.7
fIN = 170 MHz 68.6 69.1
fIN = 230 MHz 67.8 68.3
NSD Noise spectral density
(averaged across Nyquist zone)		 fIN = 10 MHz 149.3 149.5 dBFS/Hz
fIN = 70 MHz –147.5 148.8 149.0
fIN = 100 MHz 148.5 148.7
fIN = 170 MHz 147.7 148.1
fIN = 230 MHz 146.8 147.3
SINAD Signal-to-noise and distortion ratio fIN = 10 MHz 70.2 70.4 dBFS
fIN = 70 MHz 67.3 69.7 69.9
fIN = 100 MHz 69.4 68.8
fIN = 170 MHz 68.4 68.8
fIN = 230 MHz 67.5 67.8
ENOB Effective number of bits fIN = 10 MHz 11.4 11.4 Bits
fIN = 70 MHz 10.9 11.3 11.3
fIN = 100 MHz 11.2 11.3
fIN = 170 MHz 11.1 11.1
fIN = 230 MHz 10.9 10.9
SFDR Spurious-free dynamic range fIN = 10 MHz 91 88 dBc
fIN = 70 MHz 78 86 85
fIN = 100 MHz 85 84
fIN = 170 MHz 83 82
fIN = 230 MHz 81 80
HD2 Second-order harmonic distortion fIN = 10 MHz 91 92 dBc
fIN = 70 MHz 78 93 93
fIN = 100 MHz 92 93
fIN = 170 MHz 83 82
fIN = 230 MHz 81 80
HD3 Third-order harmonic distortion fIN = 10 MHz 91 88 dBc
fIN = 70 MHz 78 86 85
fIN = 100 MHz 85 84
fIN = 170 MHz 91 87
fIN = 230 MHz 87 87
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 99 95 dBc
fIN = 70 MHz 87 98 94
fIN = 100 MHz 96 94
fIN = 170 MHz 91 90
fIN = 230 MHz 91 89
THD Total harmonic distortion fIN = 10 MHz 87 85 dBc
fIN = 70 MHz 75 84 83
fIN = 100 MHz 83 82
fIN = 170 MHz 81 80
fIN = 230 MHz 78 77
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 91 91 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 86 86
DNL Differential nonlinearity fIN = 70 MHz ±0.1 ±0.1 LSBs
INL Integrated nonlinearity fIN = 70 MHz ±0.4 ±0.4 LSBs

7.9 AC Performance: ADC32J24

Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS ADC32J24 (fS = 125 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
DYNAMIC AC CHARACTERISTICS
SNR Signal-to-noise ratio fIN = 10 MHz 70.3 70.5 dBFS
fIN = 70 MHz 68.8 70.1 70.3
fIN = 100 MHz 70.1 70.2
fIN = 170 MHz 69.4 69.8
fIN = 230 MHz 68.7 69.2
NSD Noise spectral density
(averaged across Nyquist zone)		 fIN = 10 MHz 148.3 148.5 dBFS/Hz
fIN = 70 MHz –146.8 148.1 148.3
fIN = 100 MHz 148.0 148.2
fIN = 170 MHz 147.3 147.8
fIN = 230 MHz 146.7 147.2
SINAD Signal-to-noise and distortion ratio fIN = 10 MHz 70.3 70.4 dBFS
fIN = 70 MHz 67.6 70.1 70.3
fIN = 100 MHz 70.0 70.1
fIN = 170 MHz 69.2 69.6
fIN = 230 MHz 68.3 68.8
ENOB Effective number of bits fIN = 10 MHz 11.4 11.4 Bits
fIN = 70 MHz 11 11.4 11.4
fIN = 100 MHz 11.3 11.4
fIN = 170 MHz 11.2 11.3
fIN = 230 MHz 11.1 11.1
SFDR Spurious-free dynamic range fIN = 10 MHz 93 92 dBc
fIN = 70 MHz 78.5 91 90
fIN = 100 MHz 90 90
fIN = 170 MHz 85 84
fIN = 230 MHz 82 81
HD2 Second-order harmonic distortion fIN = 10 MHz 93 92 dBc
fIN = 70 MHz 78.5 91 90
fIN = 100 MHz 90 90
fIN = 170 MHz 85 84
fIN = 230 MHz 82 81
HD3 Third-order harmonic distortion fIN = 10 MHz 96 92 dBc
fIN = 70 MHz 80 95 90
fIN = 100 MHz 95 92
fIN = 170 MHz 88 86
fIN = 230 MHz 90 93
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 98 96 dBc
fIN = 70 MHz 87 99 95
fIN = 100 MHz 97 96
fIN = 170 MHz 97 94
fIN = 230 MHz 96 91
THD Total harmonic distortion fIN = 10 MHz 91 88 dBc
fIN = 70 MHz 75 89 87
fIN = 100 MHz 88 88
fIN = 170 MHz 83 82
fIN = 230 MHz 80 79
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 91 91 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 86 86
DNL Differential nonlinearity fIN = 70 MHz ±0.1 ±0.1 LSBs
INL Integrated nonlinearity fIN = 70 MHz ±0.4 ±0.4 LSBs

7.10 AC Performance: ADC32J23

Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS ADC32J23 (fS = 80 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
DYNAMIC AC CHARACTERISTICS
SNR Signal-to-noise ratio fIN = 10 MHz 70.3 70.4 dBFS
fIN = 70 MHz 68.7 70.1 70.2
fIN = 100 MHz 70.0 70.2
fIN = 170 MHz 69.6 69.9
fIN = 230 MHz 69.1 69.3
NSD Noise spectral density
(averaged across Nyquist zone)		 fIN = 10 MHz 146.3 146.4 dBFS/Hz
fIN = 70 MHz –144.8 146.2 146.3
fIN = 100 MHz 146.0 146.2
fIN = 170 MHz 145.6 145.9
fIN = 230 MHz 145.1 145.3
SINAD Signal-to-noise and distortion ratio fIN = 10 MHz 70.2 70.4 dBFS
fIN = 70 MHz 67.6 70.1 70.3
fIN = 100 MHz 70.0 70.1
fIN = 170 MHz 69.5 69.7
fIN = 230 MHz 68.7 69.0
ENOB Effective number of bits fIN = 10 MHz 11 11.4 11.4 Bits
fIN = 70 MHz 11.4 11.4
fIN = 100 MHz 11.3 11.3
fIN = 170 MHz 11.2 11.3
fIN = 230 MHz 11.1 11.1
SFDR Spurious-free dynamic range fIN = 10 MHz 96 92 dBc
fIN = 70 MHz 79.5 95 92
fIN = 100 MHz 91 88
fIN = 170 MHz 85 84
fIN = 230 MHz 81 80
HD2 Second-order harmonic distortion fIN = 10 MHz 96 95 dBc
fIN = 70 MHz 79.5 95 94
fIN = 100 MHz 94 92
fIN = 170 MHz 85 84
fIN = 230 MHz 81 80
HD3 Third-order harmonic distortion fIN = 10 MHz 98 92 dBc
fIN = 70 MHz 81 99 92
fIN = 100 MHz 91 88
fIN = 170 MHz 87 85
fIN = 230 MHz 83 82
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 99 92 dBc
fIN = 70 MHz 87 98 92
fIN = 100 MHz 97 92
fIN = 170 MHz 95 92
fIN = 230 MHz 95 92
THD Total harmonic distortion fIN = 10 MHz 93 90 dBc
fIN = 70 MHz 77 93 89
fIN = 100 MHz 88 85
fIN = 170 MHz 82 81
fIN = 230 MHz 79 78
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 90 90 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 89 89
DNL Differential nonlinearity fIN = 70 MHz ±0.1 ±0.1 LSBs
INL Integrated nonlinearity fIN = 70 MHz ±0.4 ±0.4 LSBs

7.11 AC Performance: ADC32J22

Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS ADC32J22 (fS = 50 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
DYNAMIC AC CHARACTERISTICS
SNR Signal-to-noise ratio fIN = 10 MHz 69.3 70.2 70.3 dBFS
fIN = 70 MHz 70.0 70.1
fIN = 100 MHz 69.9 70.0
fIN = 170 MHz 69.4 69.7
fIN = 230 MHz 68.0 68.1
NSD Noise spectral density
(averaged across Nyquist zone)		 fIN = 10 MHz –143.3 144.1 144.3 dBFS/Hz
fIN = 70 MHz 143.9 144.1
fIN = 100 MHz 143.8 144.0
fIN = 170 MHz 143.4 143.7
fIN = 230 MHz 141.9 142.1
SINAD Signal-to-noise and distortion ratio fIN = 10 MHz 68.1 70.1 70.2 dBFS
fIN = 70 MHz 69.9 70.0
fIN = 100 MHz 69.8 69.9
fIN = 170 MHz 69.2 69.5
fIN = 230 MHz 67.6 67.6
ENOB Effective number of bits fIN = 10 MHz 11 11.4 11.4 Bits
fIN = 70 MHz 11.3 11.3
fIN = 100 MHz 11.3 11.3
fIN = 170 MHz 11.2 11.2
fIN = 230 MHz 10.9 10.9
SFDR Spurious-free dynamic range fIN = 10 MHz 80.5 95 92 dBc
fIN = 70 MHz 94 90
fIN = 100 MHz 91 89
fIN = 170 MHz 85 85
fIN = 230 MHz 82 82
HD2 Second-order harmonic distortion fIN = 10 MHz 80.5 96 95 dBc
fIN = 70 MHz 98 97
fIN = 100 MHz 92 91
fIN = 170 MHz 85 85
fIN = 230 MHz 82 82
HD3 Third-order harmonic distortion fIN = 10 MHz 81 95 92 dBc
fIN = 70 MHz 94 90
fIN = 100 MHz 91 89
fIN = 170 MHz 88 88
fIN = 230 MHz 82 82
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 87 98 91 dBc
fIN = 70 MHz 95 92
fIN = 100 MHz 90 90
fIN = 170 MHz 96 91
fIN = 230 MHz 93 91
THD Total harmonic distortion fIN = 10 MHz 78 92 88 dBc
fIN = 70 MHz 91 87
fIN = 100 MHz 88 86
fIN = 170 MHz 83 82
fIN = 230 MHz 78 78
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 89 89 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 86 86
DNL Differential nonlinearity fIN = 70 MHz ±0.1 ±0.1 LSBs
INL Integrated nonlinearity fIN = 70 MHz ±0.4 ±0.4 LSBs

7.12 Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD = DVDD = 1.8 V and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUTS (RESET, SCLK, SEN, SDATA, PDN)(1)
VIH High-level input voltage All digital inputs support 1.8-V and 3.3-V logic levels 1.2 V
VIL Low-level input voltage All digital inputs support 1.8-V and 3.3-V logic levels 0.4 V
IIH High-level input current SEN 0 µA
RESET, SCLK, SDATA, PDN 10 µA
IIL Low-level input current SEN 10 µA
RESET, SCLK, SDATA, PDN 0 µA
DIGITAL INPUTS (SYNCP~, SYNCM~, SYSREFP, SYSREFM)
VIH High-level input voltage 1.3 V
VIL Low-level input voltage 0.5 V
V(CM_DIG) Common-mode voltage for SYNC~ and SYSREF 0.9 V
DIGITAL OUTPUTS (SDOUT, OVRA, OVRB)
VOH High-level output voltage DVDD – 0.1 DVDD V
VOL Low-level output voltage 0.1 V
DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM)(2)
VOH High-level output voltage AVDD V
VOL Low-level output voltage AVDD – 0.4 V
VOD Output differential voltage 0.4 V
VOC Output common-mode voltage AVDD – 0.2 V
Transmitter short-circuit current Transmitter pins shorted to any voltage between –0.25 V and 1.45 V –100 100 mA
zos Single-ended output impedance 50 Ω
Output capacitance Output capacitance inside the device,
from either output to ground		 2 pF
(1) The RESET, SCLK, SDATA, and PDN pins have a 150-kΩ (typical) internal pulldown resistor to ground and the SEN pin has a 150-kΩ (typical) pullup resistor to AVDD.
(2) 50-Ω, single-ended external termination to 1.8 V.

7.13 Timing Requirements

Typical values are at 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C. See Figure 143.
MIN TYP MAX UNIT
SAMPLE TIMING CHARACTERISTICS
Aperture delay 0.85 1.25 1.65 ns
Aperture delay matching between two channels on the same device ±70 ps
Aperture delay matching between two devices at the same temperature and supply voltage ±150 ps
Aperture jitter 200 fS rms
Wake-up time to valid data after coming out of STANDBY mode 35 100 µs
Wake-up time to valid data after coming out of global power-down 85 300 µs
tSU_SYNC~ Setup time for SYNC~ referenced to input clock rising edge 1 ns
tH_SYNC~ Hold time for SYNC~ referenced to input clock rising edge 100 ps
tSU_SYSREF Setup time for SYSREF referenced to input clock rising edge 1 ns
tH_SYSREF Hold time for SYSREF referenced to input clock rising edge 100 ps
CML OUTPUT TIMING CHARACTERISTICS
Unit interval 320 1667 ps
Serial output data rate 3.125 Gbps
Total jitter: 3.125 Gbps (20X mode, fS = 156.25 MSPS) 0.3 P-PUI
tR, tF Data rise time, data fall time:
rise and fall times measured from 20% to 80%, differential output waveform,
600 Mbps ≤ bit rate ≤ 3.125 Gbps		 105 ps

Table 1. Latency in Different Modes(1)(2)

MODE PARAMETER LATENCY (N Cycles) TYPICAL DATA DELAY (tD, ns)
20X ADC latency 17 0.29 × tS + 3
Normal OVR latency 9 0.5 × tS + 2
Fast OVR latency 7 0.5 × tS + 2
From SYNC~ falling edge to CGS phase(3) 15 0.3 × tS + 4
From SYNC~ rising edge to ILA sequence(4) 17 0.3 × tS + 4
40X ADC latency 16 0.85 × tS + 3.9
Normal OVR latency 9 0.5 × tS + 2
Fast OVR latency 7 0.5 × tS + 2
From SYNC~ falling edge to CGS phase(3) 14 0.9 × tS + 4
From SYNC~ rising edge to ILA sequence(4) 12 0.9 × tS + 4
(1) Overall latency = latency + tD.
(2) tS is the time period of the ADC conversion clock.
(3) Latency is specified for subclass 2. In subclass 0, the SYNC~ falling edge to CGS phase latency is 16 clock cycles in 10X mode and 15 clock cycles in 20X mode.
(4) Latency is specified for subclass 2. In subclass 0, the SYNC~ rising edge to ILA sequence latency is 11 clock cycles in 10X mode and 11 clock cycles in 20X mode.

7.14 Typical Characteristics: ADC32J25

Typical values are at TA = 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, dither enabled, and special modes written, unless otherwise noted.
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D201_SBAS668.gif
fS = 160 MSPS, SNR = 70.3 dBFS, fIN = 10 MHz,
SFDR = 92.6 dBc
Figure 1. FFT for 10-MHz Input Signal (Dither On)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D203_SBAS668.gif
fS = 160 MSPS, SNR = 69.8 dBFS, fIN = 70 MHz,
SFDR = 86 dBc
Figure 3. FFT for 70-MHz Input Signal (Dither On)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D205_SBAS668.gif
fS = 160 MSPS, SNR = 69.1 dBFS, fIN = 170 MHz,
SFDR = 83 dBc
Figure 5. FFT for 170-MHz Input Signal (Dither On)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D207_SBAS668.gif
fS = 160 MSPS, SNR = 68.1 dBFS, fIN = 270 MHz,
SFDR = 78.6 dBc
Figure 7. FFT for 270-MHz Input Signal (Dither On)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D209_SBAS668.gif
fS = 160 MSPS, SNR = 62.9 dBFS, fIN = 450 MHz,
SFDR = 66 dBc
Figure 9. FFT for 450-MHz Input Signal (Dither On)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D211_SBAS668.gif
fS = 160 MSPS, IMD = 92.3 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz
Figure 11. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D213_SBAS668.gif
fS = 160 MSPS, IMD = 82.5 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 13. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D215_SBAS668.gif
Figure 15. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D217_SBAS668.gif
Figure 17. Signal-to-Noise Ratio vs
Input Frequency
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D219_SBAS668.gif
Figure 19. Signal-to-Noise Ratio vs
Digital Gain and Input Frequency
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D221_SBAS668.gif
Figure 21. Performance vs Input Amplitude
(30 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D223_SBAS668.gif
Figure 23. Performance vs Input Common-Mode Voltage
(30 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D225_SBAS668.gif
Figure 25. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D227_SBAS668.gif
Figure 27. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D229_SBAS668.gif
Figure 29. Performance vs Clock Amplitude
(40 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D231_SBAS668.gif
Figure 31. Performance vs Clock Duty Cycle
(40 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D233_SBAS668.gif
RMS noise = 1.3 LSBs
Figure 33. Idle Channel Histogram
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D202_SBAS668.gif
fS = 160 MSPS, SNR = 70.5 dBFS, fIN = 10 MHz,
SFDR = 92.6 dBc
Figure 2. FFT for 10-MHz Input Signal (Dither Off)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D204_SBAS668.gif
fS = 160 MSPS, SNR = 70.1 dBFS, fIN = 70 MHz,
SFDR = 85 dBc
Figure 4. FFT for 70-MHz Input Signal (Dither Off)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D206_SBAS668.gif
fS = 160 MSPS, SNR = 69.3 dBFS, fIN = 170 MHz,
SFDR = 83 dBc
Figure 6. FFT for 170-MHz Input Signal (Dither Off)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D208_SBAS668.gif
fS = 160 MSPS, SNR = 68.6 dBFS, fIN = 270 MHz,
SFDR = 78.9 dBc
Figure 8. FFT for 270-MHz Input Signal (Dither Off)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D210_SBAS668.gif
fS = 160 MSPS, SNR = 63 dBFS, fIN = 450 MHz,
SFDR = 66.6 dBc
Figure 10. FFT for 450-MHz Input Signal (Dither Off)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D212_SBAS668.gif
fS = 160 MSPS, IMD = 99.3 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz
Figure 12. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D214_SBAS668.gif
fS = 160 MSPS, IMD = 98.9 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 14. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D216_SBAS668.gif
Figure 16. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D218_SBAS668.gif
Figure 18. Spurious-Free Dynamic Range vs
Input Frequency
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D220_SBAS668.gif
Figure 20. Spurious-Free Dynamic Range vs
Digital Gain and Input Frequency
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D222_SBAS668.gif
Figure 22. Performance vs Input Amplitude
(170 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D224_SBAS668.gif
Figure 24. Performance vs Input Common-Mode Voltage (170 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D226_SBAS668.gif
Figure 26. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D228_SBAS668.gif
Figure 28. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D230_SBAS668.gif
Figure 30. Performance vs Clock Amplitude
(150 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D232_SBAS668.gif
Figure 32. Performance vs Clock Duty Cycle
(150 MHz)

7.15 Typical Characteristics: ADC32J24

Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D401_SBAS668.gif
fS = 125 MSPS, SNR = 70.2 dBFS, fIN = 10 MHz,
SFDR = 99.3 dBc
Figure 34. FFT for 10-MHz Input Signal (Dither On)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D403_SBAS668.gif
fS = 125 MSPS, SNR = 70 dBFS, fIN = 70 MHz, SFDR = 91 dBc
Figure 36. FFT for 70-MHz Input Signal (Dither On)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D405_SBAS668.gif
fS = 125 MSPS, SNR = 69.3 dBFS, fIN = 170 MHz,
SFDR = 85 dBc
Figure 38. FFT for 170-MHz Input Signal (Dither On)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D407_SBAS668.gif
fS = 125 MSPS, SNR = 68.8 dBFS, fIN = 270 MHz,
SFDR = 80.5 dBc
Figure 40. FFT for 270-MHz Input Signal (Dither On)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D409_SBAS668.gif
fS = 125 MSPS, SNR = 63.5 dBFS, fIN = 450 MHz,
SFDR = 68.6 dBc
Figure 42. FFT for 450-MHz Input Signal (Dither On)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D411_SBAS668.gif
fS = 125 MSPS, IMD = 94.7 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz
Figure 44. FFT for Two-Tone Input Signal
(–7dBFS at 46 MHz and 50 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D413_SBAS668.gif
fS = 125 MSPS, IMD = 96.2 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 46. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D415_SBAS668.gif
Figure 48. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D417_SBAS668.gif
Figure 50. Signal-to-Noise Ratio vs
Input Frequency
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D419_SBAS668.gif
Figure 52. Signal-to-Noise Ratio vs
Digital Gain and Input Frequency
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D421_SBAS668.gif
Figure 54. Performance vs Input Amplitude
(30 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D423_SBAS668.gif
Figure 56. Performance vs Input Common-Mode Voltage
(30 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D425_SBAS668.gif
Figure 58. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D427_SBAS668.gif
Figure 60. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D429_SBAS668.gif
Figure 62. Performance vs Clock Amplitude
(40 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D431_SBAS668.gif
Figure 64. Performance vs Clock Duty Cycle
(40 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D433_SBAS668.gif
RMS noise = 1.4 LSBs
Figure 66. Idle Channel Histogram
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D402_SBAS668.gif
fS = 125 MSPS, SNR = 70.6 dBFS, fIN = 10 MHz,
SFDR = 93.8 dBc
Figure 35. FFT for 10-MHz Input Signal (Dither Off)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D404_SBAS668.gif
fS = 125 MSPS, SNR = 70.2 dBFS, fIN = 70 MHz,
SFDR = 90 dBc
Figure 37. FFT for 70-MHz Input Signal (Dither Off)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D406_SBAS668.gif
fS = 125 MSPS, SNR = 69.9 dBFS, fIN = 70 MHz,
SFDR = 84 dBc
Figure 39. FFT for 170-MHz Input Signal (Dither Off)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D408_SBAS668.gif
fS = 125 MSPS, SNR = 69.3 dBFS, fIN = 270 MHz,
SFDR = 79.9 dBc
Figure 41. FFT for 270-MHz Input Signal (Dither Off)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D410_SBAS668.gif
fS = 125 MSPS, SNR = 63.8 dBFS, fIN = 450 MHz,
SFDR = 68.8 dBc
Figure 43. FFT for 450-MHz Input Signal (Dither Off)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D412_SBAS668.gif
fS = 125 MSPS, IMD = 98.73 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz
Figure 45. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D414_SBAS668.gif
fS = 125 MSPS, IMD = 97 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 47. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D416_SBAS668.gif
Figure 49. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D418_SBAS668.gif
Figure 51. Spurious-Free Dynamic Range vs
Input Frequency
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D420_SBAS668.gif
Figure 53. Spurious-Free Dynamic Range vs
Digital Gain and Input Frequency
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D422_SBAS668.gif
Figure 55. Performance vs Input Amplitude
(170 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D424_SBAS668.gif
Figure 57. Performance vs Input Common-Mode Voltage (170 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D426_SBAS668.gif
Figure 59. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D428_SBAS668.gif
Figure 61. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D430_SBAS668.gif
Figure 63. Performance vs Clock Amplitude
(150 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D432_SBAS668.gif
Figure 65. Performance vs Clock Duty Cycle
(150 MHz)

7.16 Typical Characteristics: ADC32J23

Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D601_SBAS668.gif
fS = 80 MSPS, SNR = 70.1 dBFS, fIN = 10 MHz, SFDR = 95.4 dBc
Figure 67. FFT for 10-MHz Input Signal (Dither On)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D603_SBAS668.gif
fS = 80 MSPS, SNR = 70.1 dBFS, fIN = 70 MHz, SFDR = 93 dBc
Figure 69. FFT for 70-MHz Input Signal (Dither On)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D605_SBAS668.gif
fS = 80 MSPS, SNR = 69.3 dBFS, fIN = 170 MHz,
SFDR = 86 dBc
Figure 71. FFT for 170-MHz Input Signal (Dither On)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D607_SBAS668.gif
fS = 80 MSPS, SNR = 68.9 dBFS, fIN = 270 MHz,
SFDR = 76.9 dBc
Figure 73. FFT for 270-MHz Input Signal (Dither On)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D609_SBAS668.gif
fS = 80 MSPS, SNR = 62.7 dBFS, fIN = 450 MHz,
SFDR = 67.6 dBc
Figure 75. FFT for 450-MHz Input Signal (Dither On)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D611_SBAS668.gif
fS = 80 MSPS, IMD = 96 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz
Figure 77. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D613_SBAS668.gif
fS = 80 MSPS, IMD = 92.1 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 79. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D615_SBAS668.gif
Figure 81. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D617_SBAS668.gif
Figure 83. Signal-to-Noise Ratio vs
Input Frequency
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D619_SBAS668.gif
Figure 85. Signal-to-Noise Ratio vs
Digital Gain and Input Frequency
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D621_SBAS668.gif
Figure 87. Performance vs Input Amplitude
(30 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D623_SBAS668.gif
Figure 89. Performance vs Input Common-Mode Voltage
(30 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D625_SBAS668.gif
Figure 91. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D627_SBAS668.gif
Figure 93. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D629_SBAS668.gif
Figure 95. Performance vs Clock Amplitude
(40 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D631_SBAS668.gif
Figure 97. Performance vs Clock Duty Cycle
(40 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D633_SBAS668.gif
RMS noise = 1.4 LSBs
Figure 99. Idle Channel Histogram
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D602_SBAS668.gif
fS = 80 MSPS, SNR = 70.4 dBFS, fIN = 10 MHz, SFDR = 89.7 dBc
Figure 68. FFT for 10-MHz Input Signal (Dither Off)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D604_SBAS668.gif
fS = 80 MSPS, SNR = 70.3 dBFS, fIN = 70 MHz, SFDR = 92 dBc
Figure 70. FFT for 70-MHz Input Signal (Dither Off)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D606_SBAS668.gif
fS = 80 MSPS, SNR = 69.6 dBFS, fIN = 10 MHz, SFDR = 85 dBc
Figure 72. FFT for 170-MHz Input Signal (Dither Off)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D608_SBAS668.gif
fS = 80 MSPS, SNR = 69 dBFS, fIN = 270 MHz,
SFDR = 76.5 dBc
Figure 74. FFT for 270-MHz Input Signal (Dither Off)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D610_SBAS668.gif
fS = 80 MSPS, SNR = 61.8 dBFS, fIN = 450 MHz,
SFDR = 67.4 dBc
Figure 76. FFT for 450-MHz Input Signal (Dither Off)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D612_SBAS668.gif
fS = 80 MSPS, IMD = 98.5 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz
Figure 78. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D614_SBAS668.gif
fS = 80 MSPS, IMD = 97.5 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 80. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D616_SBAS668.gif
Figure 82. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D618_SBAS668.gif
Figure 84. Spurious-Free Dynamic Range vs
Input Frequency
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D620_SBAS668.gif
Figure 86. Spurious-Free Dynamic Range vs
Digital Gain and Input Frequency
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D622_SBAS668.gif
Figure 88. Performance vs Input Amplitude
(170 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D624_SBAS668.gif
Figure 90. Performance vs Input Common-Mode Voltage (170 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D626_SBAS668.gif
Figure 92. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D628_SBAS668.gif
Figure 94. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D630_SBAS668.gif
Figure 96. Performance vs Clock Amplitude
(150 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D632_SBAS668.gif
Figure 98. Performance vs Clock Duty Cycle
(150 MHz)

7.17 Typical Characteristics: ADC32J22

Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D801_SBAS668.gif
fS = 50 MSPS, SNR = 70.2 dBFS, fIN = 10 MHz, SFDR = 97.6 dBc
Figure 100. FFT for 10-MHz Input Signal (Dither On)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D803_SBAS668.gif
fS = 50 MSPS, SNR = 69.9 dBFS, fIN = 70 MHz, SFDR = 92 dBc
Figure 102. FFT for 70-MHz Input Signal (Dither On)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D805_SBAS668.gif
fS = 50 MSPS, SNR = 68.6 dBFS, fIN = 170 MHz,
SFDR = 86 dBc
Figure 104. FFT for 170-MHz Input Signal (Dither On)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D807_SBAS668.gif
fS = 50 MSPS, SNR = 68.4 dBFS, fIN = 270 MHz,
SFDR = 75.7 dBc
Figure 106. FFT for 270-MHz Input Signal (Dither On)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D809_SBAS668.gif
fS = 50 MSPS, SNR = 65.3 dBFS, fIN = 450 MHz,
SFDR = 67.4 dBc
Figure 108. FFT for 450-MHz Input Signal (Dither On)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D811_SBAS668.gif
fS = 50 MSPS, IMD = 90.2 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz
Figure 110. FFT for Two-Tone Input Signal
(–7dBFS at 46 MHz and 50 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D813_SBAS668.gif
fS = 50 MSPS, IMD = 91.2 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 112. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D815_SBAS668.gif
Figure 114. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D817_SBAS668.gif
Figure 116. Signal-to-Noise Ratio vs
Input Frequency
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D819_SBAS668.gif
Figure 118. Signal-to-Noise Ratio vs
Digital Gain and Input Frequency
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D821_SBAS668.gif
Figure 120. Performance vs Input Amplitude
(30 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D823_SBAS668.gif
Figure 122. Performance vs Input Common-Mode Voltage (30 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D825_SBAS668.gif
Figure 124. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D827_SBAS668.gif
Figure 126. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D829_SBAS668.gif
Figure 128. Performance vs Clock Amplitude
(40 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D831_SBAS668.gif
Figure 130. Performance vs Clock Duty Cycle
(40 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D833_SBAS668.gif
RMS noise = 1.3 LSBs
Figure 132. Idle Channel Histogram
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D802_SBAS668.gif
fS = 50 MSPS, SNR = 70.4 dBFS, fIN = 10 MHz, SFDR = 90.8 dBc
Figure 101. FFT for 10-MHz Input Signal (Dither Off)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D804_SBAS668.gif
fS = 50 MSPS, SNR = 70.1 dBFS, fIN = 70 MHz, SFDR = 91 dBc
Figure 103. FFT for 70-MHz Input Signal (Dither Off)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D806_SBAS668.gif
fS = 50 MSPS, SNR = 69.1 dBFS, fIN = 170 MHz,
SFDR = 85 dBc
Figure 105. FFT for 170-MHz Input Signal (Dither Off)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D808_SBAS668.gif
fS = 50 MSPS, SNR = 68.6 dBFS, fIN = 270 MHz,
SFDR = 75.6 dBc
Figure 107. FFT for 270-MHz Input Signal (Dither Off)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D810_SBAS668.gif
fS = 50 MSPS, SNR = 65.2 dBFS, fIN = 450 MHz,
SFDR = 67 dBc
Figure 109. FFT for 450-MHz Input Signal (Dither Off)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D812_SBAS668.gif
fS = 50 MSPS, IMD = 95.5 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz
Figure 111. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D814_SBAS668.gif
fS = 50 MSPS, IMD = 96.8 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 113. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D816_SBAS668.gif
Figure 115. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D818_SBAS668.gif
Figure 117. Spurious-Free Dynamic Range vs
Input Frequency
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D820_SBAS668.gif
Figure 119. Spurious-Free Dynamic Range vs
Digital Gain and Input Frequency
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D822_SBAS668.gif
Figure 121. Performance vs Input Amplitude
(170 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D824_SBAS668.gif
Figure 123. Performance vs Input Common-Mode Voltage (170 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D826_SBAS668.gif
Figure 125. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D828_SBAS668.gif
Figure 127. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D830_SBAS668.gif
Figure 129. Performance vs Clock Amplitude
(150 MHz)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D832_SBAS668.gif
Figure 131. Performance vs Clock Duty Cycle
(150 MHz)

7.18 Typical Characteristics: Common Plots

Typical values are at TA = 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
ADC32J22 ADC32J23 ADC32J24 ADC32J25 C040_BAS664.png
fS = 160 MSPS, fCM = 10 MHz, 50 mVPP, fIN = 30 MHz, Amplitude (fIN + fCM ) = –98 dBFS, Amplitude (fIN – fCM ) = –91 dBFS
Figure 133. CMRR FFT
ADC32J22 ADC32J23 ADC32J24 ADC32J25 C042_BAS664.png
fS = 160 MSPS, fPSRR = 5 MHz, 50 mVPP, fIN = 30 MHz, Amplitude (fIN + fPSRR ) = –65 dBFS, Amplitude (fIN – fPSRR ) = –67 dBFS
Figure 135. PSRR FFT for AVDD Supply
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D009_SBAS668.gif
Figure 137. Power vs Sampling Frequency
(20X Mode)
ADC32J22 ADC32J23 ADC32J24 ADC32J25 C041_BAS664.png
Figure 134. CMRR vs Test Signal Frequency
ADC32J22 ADC32J23 ADC32J24 ADC32J25 C043_BAS664.png
Figure 136. PSRR vs Test Signal Frequency
ADC32J22 ADC32J23 ADC32J24 ADC32J25 D010_SBAS668.gif
Figure 138. Power vs Sampling Frequency
(40X Mode)

7.19 Typical Characteristics: Contour Plots

Typical values are at TA = 25°C, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
ADC32J22 ADC32J23 ADC32J24 ADC32J25 SFDR_0dB_SBAS668.png
Figure 139. Spurious-Free Dynamic Range (SFDR)
for 0-dB Gain
ADC32J22 ADC32J23 ADC32J24 ADC32J25 SNR_0dB_SBAS668.png
Figure 141. Signal-to-Noise Ratio (SNR)
for 0-dB Gain
ADC32J22 ADC32J23 ADC32J24 ADC32J25 SFDR_6dB_SBAS668.png
Figure 140. Spurious-Free Dynamic Range (SFDR)
for 6-dB Gain
ADC32J22 ADC32J23 ADC32J24 ADC32J25 SNR_6dB_SBAS668.png
Figure 142. Signal-to-Noise Ratio (SNR)
for 6-dB Gain
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