10.1 Application Information

Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as ADT1-1WT or WBC1-1) can be used up to 250 MHz to achieve good phase and amplitude balances at ADC inputs. When designing the dc driving circuits, the ADC input impedance must be considered. Figure 194 and Figure 195 show the impedance (Z_in = R_in || C_in) across the ADC input pins.

Figure 194. Differential Input Resistance, R_in

Figure 195. Differential Input Capacitance, C_in

10.2 Typical Applications

10.2.1 Driving Circuit Design: Low Input Frequencies

Figure 196. Driving Circuit for Low Input Frequencies

10.2.1.1 Design Requirements

For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor in series with each input pin can be kept to damp out ringing caused by package parasitics. The drive circuit may have to be designed to minimize the affect of kick-back noise generated by sampling switches opening and closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and matched impedance to the source.

10.2.1.2 Detailed Design Procedure

A typical application using two back-to-back coupled transformers is illustrated in Figure 196. The circuit is optimized for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used. With the series inductor (39 nH), this combination helps absorb the sampling glitches.

10.2.1.3 Application Curves

Figure 197 shows the performance obtained by using the circuit illustrated in Figure 196.

fS = 160 MSPS, SNR = 72.4 dBFS, fIN = 10 MHz, SFDR = 92.3 dBc

Figure 197. FFT for 10-MHz Input Signal (Dither On)

10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz

Figure 198. Driving Circuit for Mid-Range Input Frequencies (100 MHz < f_IN < 230 MHz)

10.2.2.1 Design Requirements

See the Design Requirements section for further details.

10.2.2.2 Detailed Design Procedure

When input frequencies are between 100 MHz to 230 MHz, an R-LC-R circuit can be used to optimize performance, as shown in Figure 198.

10.2.2.3 Application Curve

Figure 199 shows the performance obtained by using the circuit shown in Figure 198.

fS = 160 MSPS, SNR = 70.6 dBFS, fIN = 170 MHz, SFDR = 94.4 dBc

Figure 199. FFT for 170-MHz Input Signal (Dither On)

10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz

Figure 200. Driving Circuit for High Input Frequencies (f_IN > 230 MHz)

10.2.3.1 Design Requirements

See the Design Requirements section for further details.

10.2.3.2 Detailed Design Procedure

For high input frequencies (> 230 MHz), using the R-C-R or R-LC-R circuit does not show significant improvement in performance. However, a series resistance of 10 Ω can be used, as shown in Figure 200.

10.2.3.3 Application Curve

Figure 201 shows the performance obtained by using the circuit shown in Figure 200.

fS = 160 MSPS, SNR = 63.2 dBFS, fIN = 450 MHz, SFDR = 65.7 dBc

Figure 201. FFT for 450-MHz Input Signal (Dither On)