9.3.1 Analog Inputs

The ADC32J4x analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-V_PP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 450 MHz (50-Ω source driving a 50-Ω termination between INP and INM).

9.3.2 Clock Input

The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 1.4 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADC32J4x can be driven by the transformer-coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in Figure 148, Figure 149, and Figure 150. See Figure 151 for details regarding the internal clock buffer.

NOTE: R_T = termination resistor, if necessary.

Figure 148. Differential Sine-Wave Clock Driving Circuit

Figure 149. LVDS Clock Driving Circuit

Figure 150. LVPECL Clock Driving Circuit

NOTE: C_EQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.

Figure 151. Internal Clock Buffer

A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 152. However, the clock inputs must be driven differentially for best performance, thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input.

Figure 152. Single-Ended Clock Driving Circuit

9.3.2.1 SNR and Clock Jitter

The signal-to-noise ratio of the ADC is limited by three different factors: quantization noise, thermal noise, and jitter noise, as shown in Equation 1. Quantization noise is typically not noticeable in pipeline converters and is
86 dB for a 14-bit ADC. Thermal noise limits SNR at low input frequencies and the clock jitter sets SNR for higher input frequencies.

Equation 1.

The SNR limitation resulting from sample clock jitter can be calculated with Equation 2:

Equation 2.

The total clock jitter (T_Jitter) has two components: the internal aperture jitter (200 fs for the device), is set by the noise of the clock input buffer, and the external clock. T_Jitter can be calculated with Equation 3:

Equation 3.

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input, although a faster clock slew rate improves ADC aperture jitter. The devices have a thermal noise of 73.5 dBFS and an internal aperture jitter of 200 fs. The SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 153.

Figure 153. SNR vs Frequency and Jitter

9.3.3 Power-Down Control

The power-down functions of the ADC32J4x can be controlled either through the parallel control pin (PDN) or through an SPI register setting (see register 15h). The PDN pin can also be configured via SPI to a global power-down or standby functionality, as shown in Table 2.

9.3.4 Internal Dither Algorithm

The ADC32J4x uses an internal dither algorithm to achieve high SFDR and a clean spectrum. However, the dither algorithm marginally degrades SNR, creating a trade-off between SNR and SFDR. If desired, the dither algorithm can be turned off by using the DIS DITH CHx registers bits. Figure 154 and Figure 155 show the effect of using dither algorithms.

fS = 160 MSPS, SNR = 72 dBFS, fIN = 70 MHz, SFDR = 95 dBc

Figure 154. FFT with Dither On

fS = 160 MSPS, SNR = 72.5 dBFS, fIN = 70 MHz, SFDR = 85 dBc

Figure 155. FFT with Dither Off

9.3.5 JESD204B Interface

The ADC32J4x support device subclass 0, 1, and 2 with a maximum output data rate of 3.2 Gbps for each serial transmitter, as shown in Figure 156. The data of each ADC are serialized by 20X using an internal PLL and then transmitted out on one differential pair each. An external SYSREF (subclass 1) or SYNC~ (subclass 2) signal is used to align all internal clock phases and the local multiframe clock to a specific sampling clock edge. This process allows synchronization of multiple devices in a system and minimizes timing and alignment uncertainty.

Figure 156. JESD204B Interface

The JESD204B transmitter block consists of the transport layer, the data scrambler, and the link layer, as shown in Figure 157. The transport layer maps the ADC output data into the selected JESD204B frame data format and determines if the ADC output data or test patterns are transmitted. The link layer performs the 8b or 10b data encoding and the synchronization and initial lane alignment using the SYNC~ input signal. Optionally, data from the transport layer can be scrambled.

Figure 157. JESD204B Block

9.3.5.3 JESD204B Frame Assembly

The JESD204B standard defines the following parameters:

• L is the number of lanes per link,
• M is the number of converters per device,
• F is the number of octets per frame clock period, and
• S is the number of samples per frame.

Table 3 lists the available JESD204B format and valid range for the ADC32J4x. The ranges are limited by the SERDES line rate and the maximum ADC sample frequency.

Table 3. LMFS Values and Interface Rate

L	M	F	S	MINIMUM ADC SAMPLING RATE (MSPS)	MAXIMUM fSERDES (Mbps)	MAXIMUM ADC SAMPLING RATE (Msps)	MAXIMUM fSERDES (GSPS)	MODE
2	2	2	1	15	300	160	3.2	20X (default)
1	2	4	1	10	400	80	3.2	40X

The detailed frame assembly for quad-channel mode is shown in Figure 158. The frame assembly configuration can be changed from 20X (default) to 40X by setting the registers listed in Table 4.

Figure 158. JESD Frame Assembly

Table 4. Configuring 40X Mode

ADDRESS	DATA
2Bh	01h
30h	11h

9.3.5.4 Digital Outputs

The ADC32J4x JESD204B transmitter uses differential CML output drivers. The CML output current is programmable from 5 mA to 20 mA using SPI register settings. The output driver expects to drive a differential 100-Ω load impedance and the termination resistors must be placed as close to the receiver inputs as possible to avoid unwanted reflections and signal distortion. Because the JESD204B employs 8b and 10b encoding, the output data stream is dc-balanced and ac-coupling can be used to avoid the need to match up common-mode voltages between the transmitter and receivers. Connect the termination resistors to the termination voltage, as shown in Figure 159.

Figure 159. CML Output Connections

Figure 160 shows the data eye measurements of the device JESD204B transmitter against the JESD204B transmitter mask at 3.125 Gbps (156.25 MSPS, 20X mode), respectively.

Figure 160. Eye Diagram: 3.125 Gbps

9.4.1 Digital Gain

The input full-scale amplitude can be selected between 1 V_PP to 2 V_PP (default is 2 V_PP) by choosing the appropriate digital gain setting via an SPI register write. Digital gain provides an option to trade-off SNR for SFDR performance. A larger input full-scale increases SNR performance (2 V_PP is recommended for maximum SNR) and a reduced input swing typically results in better SFDR performance. Table 5 lists the available digital gain settings.

9.4.2 Overrange Indication

The ADC32J4x provides two different overrange indications. The normal OVR (default) is triggered if the final 14-bit data output exceeds the maximum code value. The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and is presented after just nine clock cycles, thus enabling a quicker reaction to an overrange event. By default, the normal overrange indication is output on the OVRA, OVRB pins. The fast OVR indication can be presented on the overrange pins instead by using the SPI register map.

9.5.1 Serial Interface

The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at every SCLK rising edge when SEN is active (low). Serial data are loaded into the register at every 24th SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.

9.5.1.1 Register Initialization

After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin (of durations greater than 10 ns); see Figure 161. If required, the serial interface registers can be cleared during operation either:

1. Through a hardware reset, or
2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low.

9.5.1.1.1 Serial Register Write

The device internal register can be programmed with these steps:

1. Drive the SEN pin low,
2. Set the R/W bit to 0 (bit A15 of the 16-bit address),
3. Set bit A14 in the address field to 1,
4. Initiate a serial interface cycle by specifying the address of the register (A13 to A0) whose content must be written, and
5. Write the 8-bit data that are latched in on the SCLK rising edge.

Figure 161 and Table 6 show the timing requirements for the serial register write operation.

Figure 161. Serial Register Write Timing Diagram

Table 6. Serial Interface Timing⁽¹⁾

		MIN	TYP	MAX	UNIT
fSCLK	SCLK frequency (equal to 1 / tSCLK)	> dc		20	MHz
tSLOADS	SEN to SCLK setup time	25			ns
tSLOADH	SCLK to SEN hold time	25			ns
tDSU	SDIO setup time	25			ns
tDH	SDIO hold time	25			ns

(1) Typical values are at 25°C, full temperature range is from T_MIN = –40°C to T_MAX = 85°C, and AVDD = DVDD = 1.8 V, unless otherwise noted.

9.5.1.1.2 Serial Register Readout

The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin. This readback mode can be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. To read the contents of serial registers, follow this procedure:

1. Drive the SEN pin low.
2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers.
3. Set bit A14 in the address field to 1.
4. Initiate a serial interface cycle specifying the address of the register (A13 to A0) whose content must be read.
5. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin.
6. The external controller can latch the contents at the SCLK rising edge.
7. To enable register writes, reset the R/W register bit to 0.

When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the SDOUT pin must float. Figure 162 shows a timing diagram of the serial register read operation. Data appear on the SDOUT pin at the SCLK falling edge with an approximate delay (t_{SD_DELAY}) of 20 ns, as shown in Figure 163.

Figure 162. Serial Register Read Timing Diagram

Figure 163. SDOUT Timing Diagram

9.5.2 Register Initialization

After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin, as shown in Figure 164 and Table 7.

Figure 164. Initialization of Serial Registers after Power-Up

If required, the serial interface registers can be cleared during operation either:

1. Through hardware reset, or
2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low.

9.5.3 Start-Up Sequence

After power-up, the sequence described in Table 8 can be used to set up the ADC32J4x for basic operation.

Table 9. Register Map Summary

9.6.1 Summary of Special Mode Registers

Table 10 lists the location, value, and functions of special mode registers in the device.

9.6.2 Serial Register Descriptions