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ZHCSPO2 September 2023 ADC32RF52

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RTD|64
- MPQF141C

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RTD|64
- QFND625

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zhcspo2_oa

7.3.6.5 JESD204B Frame Assembly with Complex Decimation - Dual Band

Table 7-35 lists the available JESD204B interface formats and corresponding valid sampling rate ranges for the ADC32RF5x with complex decimation (dual band). The sampling rates are limited by the minimum and maximum SERDES line rate as well as ADC sampling clock frequencies. The JESD204B frame assembly for the different lanes are shown in Table 7-42 and Table 7-37.

Table 7-35 JESD Mode Options: Complex Decimation - Dual Band

DECIMATION SETTING D (complex)	L	M	F	S	MIN F_S (Gsps)	MAX F_S (Gsps)	RATIO [f_SERDES/(F_S/D)]
/8	8	8	2	1	0.5	1.5	20
/16					0.5
/32					0.8
/8	4	8	4	1	0.5	1.5	40
/16
/32
/64					0.8
/8	2	8	8	1	0.5	1.3	80
/16						1.5
/32
/64
/128					0.8
/16	1	8	16	1	0.5	1.3	160
/32						1.5
/64
/128

Table 7-36 JESD Sample Frame Assembly: Complex Decimation - Dual Band

OUTPUT LANE	LMFS = 8821		LMFS = 4841				LMFS = 2881
DOUT0	A1I₀ [15:8]	A1I₀ [7:0]	A1I₀ [15:8]	A1I₀ [7:0]	A1Q₀ [15:8]	A1Q₀ [7:0]	A1I₀ [15:8]	A1I₀ [7:0]	A1Q₀ [15:8]	A1Q₀ [7:0]	A2I₀ [15:8]	A2I₀ [7:0]	A2Q₀ [15:8]	A2Q₀ [7:0]
DOUT1	A1Q₀ [15:8]	A1Q₀ [7:0]	A2I₀ [15:8]	A2I₀ [7:0]	A2Q₀ [15:8]	A2Q₀ [7:0]	B1I₀ [15:8]	B1I₀ [7:0]	B1Q₀ [15:8]	B1Q₀ [7:0]	B2I₀ [15:8]	B2I₀ [7:0]	B2Q₀ [15:8]	B2Q₀ [7:0]
DOUT2	A2I₀ [15:8]	A2I₀ [7:0]	B1I₀ [15:8]	B1I₀ [7:0]	B1Q₀ [15:8]	B1Q₀ [7:0]
DOUT3	A2Q₀ [15:8]	A2Q₀ [7:0]	B2I₀ [15:8]	B2I₀ [7:0]	B2Q₀ [15:8]	B2Q₀ [7:0]
DOUT4	B1I₀ [15:8]	B1I₀ [7:0]
DOUT5	B1Q₀ [15:8]	B1Q₀ [7:0]
DOUT6	B2I₀ [15:8]	B2I₀ [7:0]
DOUT7	B2Q₀ [15:8]	B2Q₀ [7:0]

Table 7-37 JESD Sample Frame Assembly: Complex Decimation - Dual Band

OUTPUT LANE	LMFS = 1-8-16-1
DOUT0	A1I₀ [15:8]	A1I₀ [7:0]	A1Q₀ [15:8]	A1Q₀ [7:0]	A2I₀ [15:8]	A2I₀ [7:0]	A2Q₀ [15:8]	A2Q₀ [7:0]	B1I₀ [15:8]	B1I₀ [7:0]	B1Q₀ [15:8]	B1Q₀ [7:0]	B2I₀ [15:8]	B2I₀ [7:0]	B2Q₀ [15:8]	B2Q₀ [7:0]
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7