ZHCSPO2 September   2023 ADC32RF52

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (Dither DISABLED)
    8. 6.8  Electrical Characteristics - AC Specifications (Dither ENABLED)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 功能方框图
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth and Full-Scale
        2. 7.3.1.2 Input Imbalance
        3. 7.3.1.3 Overrange Indication
        4. 7.3.1.4 Analog out-of-band dither
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Capture Detection
      4. 7.3.4 ADC Foreground Calibration
        1. 7.3.4.1 Calibration Control
        2. 7.3.4.2 ADC Switch
        3. 7.3.4.3 Calibration Configuration
      5. 7.3.5 Decimation Filter
        1. 7.3.5.1 Decimation Filter Response
        2. 7.3.5.2 Decimation Filter Configuration
        3. 7.3.5.3 20-bit Output Mode
        4. 7.3.5.4 Dynamic Switching
          1. 7.3.5.4.1 2 Lane Mode
          2. 7.3.5.4.2 1 Lane Mode
        5. 7.3.5.5 Numerically Controlled Oscillator (NCO)
        6. 7.3.5.6 NCO Frequency Programming
        7. 7.3.5.7 Fast Frequency Hopping
          1. 7.3.5.7.1 Fast frequency hopping using the GPIO1/2 pins
          2. 7.3.5.7.2 Fast frequency hopping using GPIO1/2, SEN and SDATA pins
          3. 7.3.5.7.3 Fast frequency hopping using the fast SPI
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 7.3.6.1.1 SYNC Signal
        2. 7.3.6.2 JESD204B Frame Assembly
        3. 7.3.6.3 JESD204B Frame Assembly in Bypass Mode
        4. 7.3.6.4 JESD204B Frame Assembly with Complex Decimation - Single Band
        5. 7.3.6.5 JESD204B Frame Assembly with Complex Decimation - Dual Band
        6. 7.3.6.6 JESD204B Frame Assembly with Complex Decimation - Quad Band
      7. 7.3.7 SERDES Output MUX
      8. 7.3.8 Test Pattern
        1. 7.3.8.1 Transport Layer
        2. 7.3.8.2 Link Layer
        3. 7.3.8.3 Internal Capture Memory Buffer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Averaging
    5. 7.5 Programming
      1. 7.5.1 GPIO Pin Control
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Description
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Sampling Clock
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Initial Device Configuration After Power-Up
        1. 8.3.1.1  STEP 1: RESET
        2. 8.3.1.2  STEP 2: Device Configuration
        3. 8.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 8.3.1.4  STEP 4: SYSREF Synchronization
        5. 8.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 8.3.1.6  STEP 6: Analog Trim Settings
        7. 8.3.1.7  STEP 7: Calibration Configuration
        8. 8.3.1.8  STEP 8: SYSREF Synchronization
        9. 8.3.1.9  STEP 9: Run Power up Calibration
        10. 8.3.1.10 STEP 10: JESD Interface Synchronization
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.1.2 STEP 2: Device Configuration

In this step, the operating mode and digital features (DDC, test pattern) are configured.

Table 8-5 Register Programming Sequence for Device Configuration
ADDRESS DATA DESCRIPTION
0x05 0x20 Select CALIBRATION page
0x34 0x03 Select 2x averaging (1x AVG: 0x01, 4x AVG: 0x07)
0x05 0x02 Select DIGITAL page
0x2C 0x01 Select DDC Bypass mode
0x2D 0x00 No decimation, step can be skipped
0x2E 0x0B Select 2x averaging (1x: 0x09, 2x: 0x0B, 4x: 0x0D), OVR on JESD
0x23C 0x07 Set register to 0x07
0x33 0x10 Set register to 0x10
0x2F 0x11 Set register to 0x11 (1x: 0x55, 2x: 0x11, 4x: 0xE1)
0x30 0x11 Set register to 0x11 (1x: 0x55, 2x: 0x11, 4x: 0xE1)
0x05 0x40 Select ANALOG page
0x7B/8B 0x00 Select internal input termination (0x00 = 100 Ω)
0xA8 0x00 DITHER AMP1: 3 = 0x80, 0 = 0x00
0xCD 0x00 DITHER AMP2: -4 = 0x40, 0 = 0x00
0x04 0x01
0x20 0x04
0x91 0x40
0xAF 0x10
0xB1 0x00 Sets dither divider. 0x00 = /50
0xB2 0x00
0xAF 0x18
0xAF 0x10 0x10 = dither ENABLED, 0x90 = dither DISABLED
0x04 0x01
0x20 0x00
0x04 0x00
0x05 0x02
0x363 0x01
0x05 0x18 Select DDCA and DDCB pages, load non linearity correction (NLC) trims
0x21D 0x00
0x21E 0x01
0x205 0x03
0x204 0xFF
0x31D 0x00
0x31E 0x01
0x305 0x03
0x304 0xFF
0x31C 0x3E
0x325 0x00 Load NLC
0x325 0x01
0x325 0x00
Sampling Rate 640 - 1500 MSPS
Nyquist Zone 1st 2nd
0x206 0x0E 0x0F
0x207 0x00 0x00
0x208 0x00 0x00
0x209 0x00 0x00
0x20A 0xF5 0xF4
0x20B 0x03 0x03
0x20C 0x27 0x28
0x20D 0x00 0x00
0x210 0xFC 0F9
0x211 0x03 0x03
0x212 0x5F 0xFD
0x213 0x03 0x03
0x21A 0x3C 0x3D
0x21C 0x00 0x00
0x223 0xFF 0xFF
0x224 0xFF 0xFF
0x225 0x00 Load NLC
0x225 0x01
0x225 0x00
0x20 0x02 OVR MUX EN
0x203 0x30
0x303 0x30
0x180 0x30
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