To maximize the SNR performance of the ADC a very low jitter (< 50 fs) sampling clock is required. Figure 8-96 shows the estimated SNR performance vs input frequency vs external clock jitter. The internal ADC aperture jitter also has some depenceny to the clock amplitude (gets more sensitive with higher input frequency) as shown in Figure 8-97.

When using averaging and/or decimation, the SNR for a single ADC core should be estimated first before adding the SNR improvement from internal averaging and/or decimation.