The internal sampling clock path was designed for lowest residual phase noise contribution. The sampling clock circuitry requires a dedicated low noise power supply for best performance. The internal residual clock phase noise is also sensitive to clock amplitude and for best performance the clock amplitude should be larger than
1 V_PP.

The clock input and ADC sampling circuitry also have an amplitude noise component which modulates on to the sampled input signal. Unlike phase noise, the amplitude noise does not scale with input frequency as shown in Figure 7-8. This noise component can dominate the close in noise performance at lower input frequencies.

Figure 7-8 Amplitude Noise

The internal aperture jitter is also dependent on the amplitude of the external clock input signal. Figure 7-9 and Figure 7-10 show the expected SNR performance with dither on/off across clock amplitude.

Figure 7-9 SNR vs Clock Amplitude (F_IN = 900 MHz)

Figure 7-10 SNR vs Clock Amplitude (F_IN = 1800 MHz)

The sampling clock input is internally terminated to 100 Ω differentially and provides a return loss better than 10 dB (see Figure 7-11). The clock input consists of a single clock input buffer followed by a dedicated clock buffer for ADCA1/2 as well as ADCB1/2. When averaging multiple ADCs, there are some close in clock buffer noise which is correlated; and thus, does not improve with averaging.

Figure 7-11 Clock Input Internal Circuitry