ZHCSPO2 September   2023 ADC32RF52

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (Dither DISABLED)
    8. 6.8  Electrical Characteristics - AC Specifications (Dither ENABLED)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 功能方框图
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth and Full-Scale
        2. 7.3.1.2 Input Imbalance
        3. 7.3.1.3 Overrange Indication
        4. 7.3.1.4 Analog out-of-band dither
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Capture Detection
      4. 7.3.4 ADC Foreground Calibration
        1. 7.3.4.1 Calibration Control
        2. 7.3.4.2 ADC Switch
        3. 7.3.4.3 Calibration Configuration
      5. 7.3.5 Decimation Filter
        1. 7.3.5.1 Decimation Filter Response
        2. 7.3.5.2 Decimation Filter Configuration
        3. 7.3.5.3 20-bit Output Mode
        4. 7.3.5.4 Dynamic Switching
          1. 7.3.5.4.1 2 Lane Mode
          2. 7.3.5.4.2 1 Lane Mode
        5. 7.3.5.5 Numerically Controlled Oscillator (NCO)
        6. 7.3.5.6 NCO Frequency Programming
        7. 7.3.5.7 Fast Frequency Hopping
          1. 7.3.5.7.1 Fast frequency hopping using the GPIO1/2 pins
          2. 7.3.5.7.2 Fast frequency hopping using GPIO1/2, SEN and SDATA pins
          3. 7.3.5.7.3 Fast frequency hopping using the fast SPI
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 7.3.6.1.1 SYNC Signal
        2. 7.3.6.2 JESD204B Frame Assembly
        3. 7.3.6.3 JESD204B Frame Assembly in Bypass Mode
        4. 7.3.6.4 JESD204B Frame Assembly with Complex Decimation - Single Band
        5. 7.3.6.5 JESD204B Frame Assembly with Complex Decimation - Dual Band
        6. 7.3.6.6 JESD204B Frame Assembly with Complex Decimation - Quad Band
      7. 7.3.7 SERDES Output MUX
      8. 7.3.8 Test Pattern
        1. 7.3.8.1 Transport Layer
        2. 7.3.8.2 Link Layer
        3. 7.3.8.3 Internal Capture Memory Buffer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Averaging
    5. 7.5 Programming
      1. 7.5.1 GPIO Pin Control
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Description
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Sampling Clock
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Initial Device Configuration After Power-Up
        1. 8.3.1.1  STEP 1: RESET
        2. 8.3.1.2  STEP 2: Device Configuration
        3. 8.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 8.3.1.4  STEP 4: SYSREF Synchronization
        5. 8.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 8.3.1.6  STEP 6: Analog Trim Settings
        7. 8.3.1.7  STEP 7: Calibration Configuration
        8. 8.3.1.8  STEP 8: SYSREF Synchronization
        9. 8.3.1.9  STEP 9: Run Power up Calibration
        10. 8.3.1.10 STEP 10: JESD Interface Synchronization
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Mechanical, Packaging, and Orderable Information

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8.3.1.6 STEP 6: Analog Trim Settings

The following registers need to be set for best analog performance. The register write order is all writes in first 2 columns before moving to the next set of address/data in middle columns, and so on.

Table 8-9 Analog Trim Setting Registers
ADDRDATAADDRDATAADDRDATA
0x050x400xA81x AVG: 0x18
2x/4x AVG:
FS<1.1 GSPS: 0x00
FS=1.1-1.5 GSPS: 0x08		0x560x0F
0xE80xF00x6E0x08
0xE90x010x1020x02
0x4B0x1F0xCD0x000x1030xD9
0x5B0x010xCE0x000xA70x00
0xEA0x000x100See Table 8-10 for sample rate dependent trim registers0xA60x08
0xEB0x030x1010x050x20
0x950x000x1040xC90x09
0xFC0x280x1050x1020xFE
0xE00x8E0x1070x100x1030x03
0xE10x030x050x200x1040xD4
0x4C0x400x300xE80x1050x03
0x4E0x010x310xFF0x1060xFE
0x4E0x000x300x080x1070x03
0xA10x010x310x800x1080xBC
0xF80x000x320x030x1090x1A
0x310x200x050x020x1010x01
0xFD0x1C0x2430x020x1590x63
0xAA0x020x050x200x050x40
0x4D0x800x360x040x310x00
0xB30x300x1F80x010x4D0x00
0x640x100x1FC0x0A0x620x10
0x620x120x1F00x200x560x0E
0xFE0x800x1F10x0C0x560x0C
0xFC0x280x050x400x560x08
0xFF0x140x390x400x560x00
0x1060x000x560x010x6E0x00
0x1070x000x560x030xF80x06
0x3B0x0C0x560x07
Table 8-10 Sample rate dependent trim registers
FS (GSPS)0x1000x1010x1040x105
0.6-0.70x480x000x010x01
0.7-0.90xC80x010x810x00
0.9-1.10x480x010x810x00
1.1-1.30xC80x000x810x00
1.3-1.50x480x000x810x00
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