Figure 7-16 shows a timing diagram of the calibration control using GPIO1 pin.

When GPIO1 transitions to LOW logic state:

• an ADC pair gets swapped out within ~ 120 ns
• a new calibration gets triggered immediately

If GPIO1 is being held low when the calibration of an ADC pair is completed, the next ADC pair is switched and a new calibration is triggered. The order in which ADC pair gets calibrated can be configured via SPI to serial or random.

When using 2x averaging for example, the calibration is executed for 3 ADC pairs to make sure all ADCs in use have been recently calibrated.

Figure 7-16 Timing diagram - calibration (4x AVG example)

Figure 7-17 shows the ADC switch happens approximate 120 ns after the logic level change on GPIO1 is detected.

Figure 7-17 Timing diagram shows the ADC switch