ZHCSPO2 September   2023 ADC32RF52

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (Dither DISABLED)
    8. 6.8  Electrical Characteristics - AC Specifications (Dither ENABLED)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 功能方框图
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth and Full-Scale
        2. 7.3.1.2 Input Imbalance
        3. 7.3.1.3 Overrange Indication
        4. 7.3.1.4 Analog out-of-band dither
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Capture Detection
      4. 7.3.4 ADC Foreground Calibration
        1. 7.3.4.1 Calibration Control
        2. 7.3.4.2 ADC Switch
        3. 7.3.4.3 Calibration Configuration
      5. 7.3.5 Decimation Filter
        1. 7.3.5.1 Decimation Filter Response
        2. 7.3.5.2 Decimation Filter Configuration
        3. 7.3.5.3 20-bit Output Mode
        4. 7.3.5.4 Dynamic Switching
          1. 7.3.5.4.1 2 Lane Mode
          2. 7.3.5.4.2 1 Lane Mode
        5. 7.3.5.5 Numerically Controlled Oscillator (NCO)
        6. 7.3.5.6 NCO Frequency Programming
        7. 7.3.5.7 Fast Frequency Hopping
          1. 7.3.5.7.1 Fast frequency hopping using the GPIO1/2 pins
          2. 7.3.5.7.2 Fast frequency hopping using GPIO1/2, SEN and SDATA pins
          3. 7.3.5.7.3 Fast frequency hopping using the fast SPI
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 7.3.6.1.1 SYNC Signal
        2. 7.3.6.2 JESD204B Frame Assembly
        3. 7.3.6.3 JESD204B Frame Assembly in Bypass Mode
        4. 7.3.6.4 JESD204B Frame Assembly with Complex Decimation - Single Band
        5. 7.3.6.5 JESD204B Frame Assembly with Complex Decimation - Dual Band
        6. 7.3.6.6 JESD204B Frame Assembly with Complex Decimation - Quad Band
      7. 7.3.7 SERDES Output MUX
      8. 7.3.8 Test Pattern
        1. 7.3.8.1 Transport Layer
        2. 7.3.8.2 Link Layer
        3. 7.3.8.3 Internal Capture Memory Buffer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Averaging
    5. 7.5 Programming
      1. 7.5.1 GPIO Pin Control
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Description
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Sampling Clock
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Initial Device Configuration After Power-Up
        1. 8.3.1.1  STEP 1: RESET
        2. 8.3.1.2  STEP 2: Device Configuration
        3. 8.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 8.3.1.4  STEP 4: SYSREF Synchronization
        5. 8.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 8.3.1.6  STEP 6: Analog Trim Settings
        7. 8.3.1.7  STEP 7: Calibration Configuration
        8. 8.3.1.8  STEP 8: SYSREF Synchronization
        9. 8.3.1.9  STEP 9: Run Power up Calibration
        10. 8.3.1.10 STEP 10: JESD Interface Synchronization
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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7.3.7 SERDES Output MUX

The SERDES output block contains one digital mux per SERDES output lane with a 3-bit register. This allows routing any of the 8 digital streams to any output serdes transmitter as shown in the example in Figure 7-40. The MUX can be used to reorder lanes as well as duplicate lane outputs (for example in LMFS = 1-4-8-1 mode the same output stream could be duplicated on all 8 lanes).

GUID-20220427-SS0I-GJ2Z-SC0Q-DH4B2LPXHM80-low.svg Figure 7-40 SERDES output mux for DOUT0

By default after power the active SERDES lanes start on lane DOUT0 as shown for the complex decimation dual band example in Table 7-42. After power up the output is transmitted on lanes DOUT0..3. Using the digital output muxes, the output data for channel B is shifted from lanes DOUT2,3 to DOUT4,5. All SERDES transmitters are powered up and enabled by default. After configuring the output mux unused lanes can be powered down to save power consumption.

Table 7-42 JESD Sample Frame Assembly: Complex Decimation - Dual Band with LMFS = 4841
OUTPUT
LANE		DefaultUsing MUX
DOUT0A1I0 [15:8]A1I0 [7:0]A1Q0 [15:8]A1Q0 [7:0]A1I0 [15:8]A1I0 [7:0]A1Q0 [15:8]A1Q0 [7:0]
DOUT1A2I0 [15:8]A2I0 [7:0]A2Q0 [15:8]A2Q0 [7:0]A2I0 [15:8]A2I0 [7:0]A2Q0 [15:8]A2Q0 [7:0]
DOUT2B1I0 [15:8]B1I0 [7:0]B1Q0 [15:8]B1Q0 [7:0]
DOUT3B2I0 [15:8]B2I0 [7:0]B2Q0 [15:8]B2Q0 [7:0]
DOUT4B1I0 [15:8]B1I0 [7:0]B1Q0 [15:8]B1Q0 [7:0]
DOUT5B2I0 [15:8]B2I0 [7:0]B2Q0 [15:8]B2Q0 [7:0]
DOUT6
DOUT7

Table 7-43 shows the register writes to shift the output lanes from default as illustrated in Table 7-42.

Table 7-43 Example register writes to shift the output serdes lanes using the SERDES Output MUX
ADDRDATADESCRIPTION
0x050x04Select JESD page
0x810x54Select internal JESD streams 4 and 5 to lanes DOUT2 and DOUT3
0x820x32Select internal JESD streams 2 and 3 to lanes DOUT4 and DOUT5
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