The ADC32RF5x provides two different options to output test patterns instead of the actual output data of the ADC in order to simplify the serial interface and system debug of the JESD204B digital interface link. The output data path is shown in Figure 7-44.

Figure 7-44 Test Pattern Options

The available test patterns in each block are described in Table 7-47. Both test pattern blocks replace output data from the digital block, and not from the ADC; therefore, it is available in decimation or decimation bypass mode. The test patterns are synchronized with the SYSREF signal.

The RAMP pattern provides two different output options. Internally each ADC data bus consists of parallel data streams (1 stream per serdes lane). The RAMP pattern is generated for each stream and a different starting value can be set for each stream. By default, the starting values are 0. For example, a LMFS mode using 4 lanes/ADC would show a slow ramp which increments once every 4 clock cycles with starting values set to 0 and ramp increment = 1. Also, a RAMP pattern which increments every clock cycle can be set using different starting values (such as 0, 1, 2, 3) for the 4 streams/lanes and setting the RAMP increment to 4. The follow table shows how to enable the RAMP test pattern.