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7.3.2 Sampling Clock Input

The internal sampling clock path was designed for lowest residual phase noise contribution. The sampling clock circuitry requires a dedicated low noise power supply for best performance. The internal residual clock phase noise is also sensitive to clock amplitude. For best performance, the clock amplitude should be larger than 1 V_PP. The phase noise ideally improves by 3 dB per 2x averaging, however at higher input frequencies the clock path contribution reduces the improvement.

Table 7-7 Internal Aperture Clock Phase Noise
(F_S = 3 Gsps, V_IN = 1 V_PP)

Frequency Offset (MHz)	Amplitude (dBc/Hz)
0.001	-117
0.01	-127
0.1	-137
1	-147
10	-154
250	-160

The clock input and ADC sampling circuitry also have an amplitude noise component which modulates on to the sampled input signal. Unlike phase noise, the amplitude noise does not scale with input frequency, it is only affected by the sampling reset switch as shown in Figure 7-10 and Figure 7-11. This noise component can dominate the close in noise performance at lower input frequencies.

Figure 7-10 Amplitude Noise vs Input Frequency

Figure 7-11 Amplitude and Phase noise at 10 kHz offset vs Input Frequency

The internal aperture jitter is also dependent on the amplitude of the external clock input signal. Figure 7-12 and Figure 7-13 show the expected SNR performance with dither on/off across clock amplitude (F_S = 2.6 GSPS).

Figure 7-12 SNR vs Clock Amplitude (Dither OFF)

Figure 7-13 SNR vs Clock Amplitude (Dither ON)

The sampling clock input is internally terminated to 100 Ω differentially and provides a return loss better than 10 dB at 3 GHz (see Figure 7-14). The clock input consists of a single clock input buffer followed by a dedicated clock buffer for ADCA1/2 as well as ADCB1/2. When averaging multiple ADCs, there are some close in clock buffer noise which is correlated; and thus, does not improve with averaging.

Figure 7-14 Internal Clock Input Routing