The device clock inputs must be AC-coupled to the device to provide the rated performance. The clock source must have low jitter (integrated phase noise) for the ADC to meet the stated SNR performance, especially when operating at higher input frequencies. The clock signal may need to be filtered with a band pass filter in order to remove some of the broad band clock noise.

The JESD204B data converter system (ADC and FPGA) requires additional SYSREF and device clocks. The LMK04828 or LMK04832 devices are suitable to generate these clocks. Depending on the ADC clock frequency and jitter requirements. The device may also be used as a system clock synthesizer or as a device clock and SYSREF distribution device when using multiple ADC32RF5x devices in a system.