The ADC32RF8x analog signal inputs are designed to be driven differentially. The analog input pins have internal analog buffers that drive the sampling circuit. The ADC32RF8x provides on-chip, differential termination to minimize reflections. The buffer also helps isolate the external driving circuit from the internal switching currents of the sampling circuit, thus resulting in a more constant SFDR performance across input frequencies.

The common-mode voltage of the signal inputs is internally biased to CM using the 32.5-Ω termination resistors that allow for ac-coupling of the input drive network. Figure 8-1 and Figure 8-2 show SDD11 at the analog inputs from dc to 5 GHz with a 100-Ω reference impedance.

Figure 8-1 Equivalent Input Impedance

Figure 8-2 SDD11 Over the Input Frequency Range

The input impedance of analog inputs can also be modeled as parallel combination of equivalent resistance and capacitance. Figure 8-3 and Figure 8-4 show how equivalent impedance (C_IN and R_IN) vary over frequency.

Figure 8-3 Differential Input Capacitance vs. Input Frequency

Figure 8-4 Differential Input Resistance vs. Input Frequency

Each input pin (INP, INM) must swing symmetrically between (CM + 0.3375 V) and (CM – 0.3375 V), resulting in a 1.35-V_PP (default) differential input swing. As shown in Figure 8-5, the input sampling circuit has a 3-dB bandwidth that extends up to approximately 3.2 GHz.

Figure 8-5 Input Bandwidth With a 100-Ω Source Resistance