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ZHCSFU8B May 2016 – December 2021 ADC32RF80 , ADC32RF83

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机械数据 (封装 | 引脚)

RMP|72
- MPQF396A
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- MPQF526

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8.4.3 Serial Interface

The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDIN (serial interface data) pins. Serially shifting bits into the device is enabled when SEN is low. SDIN serial data are latched at every SCLK rising edge when SEN is active (low), as shown in Figure 8-56. The interface can function with SCLK frequencies from 20 MHz down to low speeds (of a few hertz) and also with a non-50% SCLK duty cycle, as shown in Table 8-25.

The SPI access uses 24 bits consisting of eight register data bits, 12 register address bits, and four special bits to distinguish between read/write, page and register, and individual channel access, as described in Table 8-26.

Figure 8-56 SPI Timing Diagram

Table 8-25 SPI Timing Information

		MIN	TYP	MAX	UNIT
f_SCLK	SCLK frequency (equal to 1 / t_SCLK)	1		20	MHz
t_SLOADS	SEN to SCLK setup time	50			ns
t_SLOADH	SCLK to SEN hold time	50			ns
t_DSU	SDIN setup time	10			ns
t_DH	SDIN hold time	10			ns
t_SDOUT	Delay between SCLK falling edge to SDOUT		10		ns

Table 8-26 SPI Input Description

SPI BIT	DESCRIPTION	OPTIONS
R/W bit	Read/write bit	0 = SPI write 1 = SPI read back
M bit	SPI bank access	0 = Analog SPI bank (master) 1 = All digital SPI banks (main digital, interleaving, decimation filter, JESD digital, and so forth)
P bit	JESD page selection bit	0 = Page access 1 = Register access
CH bit	SPI access for a specific channel of the JESD SPI bank	0 = Channel A 1 = Channel B
ADDR[11:0]	SPI address bits	—
DATA[7:0]	SPI data bits	—

Figure 8-57 shows the SDOUT timing when data are read back from a register. Data are placed on the SDOUT bus at the SCLK falling edge so that the data can be latched at the SCLK rising edge by the external receiver.

Figure 8-57 SDOUT Timing