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ZHCSFU8B May 2016 – December 2021 ADC32RF80 , ADC32RF83

PRODUCTION DATA

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机械数据 (封装 | 引脚)

RMP|72
- MPQF396A
RRH|72
- MPQF526

散热焊盘机械数据 (封装 | 引脚)

订购信息

6.10 Timing Requirements

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, 50% clock duty cycle, DDC-bypassed performance, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)

		MIN	NOM	MAX	UNIT
SAMPLE TIMING
	Aperture delay	250		750	ps
	Aperture delay matching between two channels on the same device		±15		ps
	Aperture delay matching between two devices at the same temperature and supply voltage		±150		ps
	Aperture jitter, clock amplitude = 2 V_PP		90		f_S
Latency ⁽¹⁾⁽³⁾	Data latency, ADC sample to digital output, DDC block bypassed⁽⁴⁾, LMFS = 8224		424		Input clock cycles
	Fast overrange latency, ADC sample to FOVR indication on GPIO pins		70
t_PD	Propagation delay time: logic gates and output buffer delay (does not change with f_S)		6		ns
SYSREF TIMING⁽²⁾
t_{SU_SYSREF}	SYSREF setup time: referenced to clock rising edge, 2949.12 MSPS	140	70		ps
t_{H_SYSREF}	SYSREF hold time: referenced to clock rising edge, 2949.12 MSPS	50	20		ps
	Valid transition window sampling period: t_{SU_SYSREF} – t_{H_SYSREF}, 2949.12 MSPS	143			ps
JESD OUTPUT INTERFACE TIMING
UI	Unit interval: 12.5 Gbps	80	100	400	ps
	Serial output data rate	2.5	10.0	12.5	Gbps
	Rise, fall times: 1-pF, single-ended load capacitance to ground		60		ps
	Total jitter: BER of 1E-15 and lane rate = 12.5 Gbps		25		%UI
	Random jitter: BER of 1E-15 and lane rate = 12.5 Gbps		0.99		%UI, rms
	Deterministic jitter: BER of 1E-15 and lane rate = 12.5 Gbps		9.1		%UI, pk-pk

(1) Overall latency = latency + t_PD.

(2) Common-mode voltage for the SYSREF input is kept at 1.2 V.

(3) Latency increases when the DDC modes are used; see Table 8-5.

(4) For latency in different DDC options, see Table 8-5.

V_OCM is not the same as V_ICM. Similarly, V_OD is not the same as V_ID.

Figure 6-1 Logic Levels for Digital Inputs and Outputs

Figure 6-2 SYSREF Timing Diagram