The receiving device starts the initial lane alignment process by deasserting the SYNCB signal. The SYNCB signal can be issued using the SYNCB input pins or by setting the proper SPI bits. When a logic low is detected on the SYNCB input, the ADC32RF8x starts transmitting comma (K28.5) characters to establish the code group synchronization, as shown in Figure 8-55.

When synchronization completes, the receiving device reasserts the SYNCB signal and the ADC32RF8x starts the initial lane alignment sequence with the next local multiframe clock boundary. The ADC32RF8x transmits four multiframes, each containing K frames (K is SPI programmable). Each of the multiframes contains the frame start and end symbols. The second multiframe also contains the JESD204 link configuration data.

Figure 8-55 JESD Internal Timing Information