10.1 Application Information

Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as ADT1-1WT or WBC1-1) may be used up to 250 MHz to achieve good phase and amplitude balances at ADC inputs. While designing the dc driving circuits, the ADC input impedance must be considered. Figure 195 and Figure 196 show the impedance (Z_in = R_in || C_in) across the ADC input pins.

Figure 195. Differential Input Resistance, R_IN

Figure 196. Differential Input Capacitance, C_IN

10.2 Typical Applications

10.2.1 Driving Circuit Design: Low Input Frequencies

Figure 197. Driving Circuit for Low Input Frequencies

10.2.1.1 Design Requirements

For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor in series with each input pin may be kept to damp out ringing caused by package parasitic. The drive circuit may have to be designed to minimize the impact of kick-back noise generated by sampling switches opening and closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and matched impedance to the source.

10.2.1.2 Detailed Design Procedure

A typical application involving using two back-to-back coupled transformers is shown in Figure 197. The circuit is optimized for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used with the series inductor (39 nH), this combination helps absorb the sampling glitches. To improve phase and amplitude balance of first transformer, the termination resistors can be split between two transformers. For example, 25-Ω to 25-Ω termination across the secondary winding of the second transformer can be changed to 50-Ω to 50-Ω termination and another 50-Ω to 50-Ω resistor can be placed inside the dashed box between the transformers in Figure 197.

10.2.1.3 Application Curve

Figure 198 shows the performance obtained by using the circuit shown in Figure 197.

SFDR = 95 dBc, SNR = 72.7 dBFS, SINAD = 72.6 dBFS, THD = 100 dBc, HD2 = 95 dBc, HD3 = 96 dBc

Figure 198. FFT for 10-MHz Input Signal
(Chopper On, Dither On)

10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz

Figure 199. Driving Circuit for Mid-Range Input Frequencies (100 MHz < f_IN < 230 MHz)

10.2.2.1 Design Requirements

See the Design Requirements section for further details.

10.2.2.2 Detailed Design Procedure

When input frequencies are between 100 MHz to 230 MHz, an R-LC-R circuit may be used to optimize performance, as shown in Figure 199.

10.2.2.3 Application Curve

Figure 200 shows the performance obtained by using the circuit shown in Figure 199.

SFDR = 86 dBc, SNR = 71.7 dBFS, SINAD = 71.6 dBFS, THD = 93 dBc, HD2 = 86 dBc, HD3 = 99 dBc

Figure 200. FFT for 170-MHz Input Signal (Chopper Off, Dither On)

10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz

Figure 201. Driving Circuit for High Input Frequencies (f_IN > 230 MHz)

10.2.3.1 Design Requirements

See the Design Requirements section for further details.

10.2.3.2 Detailed Design Procedure

For high input frequencies (> 230 MHz), using the R-C-R or R-LC-R circuit does not show significant improvement in performance. However, a series resistance of 10 Ω may be used as shown in Figure 201.

10.2.3.3 Application Curve

Figure 202 shows the performance obtained by using the circuit shown in Figure 201.

SFDR = 72 dBc, SNR = 68.2 dBFS, SINAD = 67.3 dBFS, THD = 74 dBc, HD2 = 72 dBc, HD3 = 79 dBc

Figure 202. FFT for 450-MHz Input Signal (Chopper Off, Dither On)