ZHCSE80B July   2014  – April 2017 ADC3441 , ADC3442 , ADC3443 , ADC3444

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: General
    6. 7.6  Electrical Characteristics: ADC3441, ADC3442
    7. 7.7  Electrical Characteristics: ADC3443, ADC3444
    8. 7.8  AC Performance: ADC3441
    9. 7.9  AC Performance: ADC3442
    10. 7.10 AC Performance: ADC3443
    11. 7.11 AC Performance: ADC3444
    12. 7.12 Digital Characteristics
    13. 7.13 Timing Requirements: General
    14. 7.14 Timing Requirements: LVDS Output
    15. 7.15 Typical Characteristics: ADC3441
    16. 7.16 Typical Characteristics: ADC3442
    17. 7.17 Typical Characteristics: ADC3443
    18. 7.18 Typical Characteristics: ADC3444
    19. 7.19 Typical Characteristics: Common
    20. 7.20 Typical Characteristics: Contour
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Inputs
      2. 9.3.2 Clock Input
        1. 9.3.2.1 Using the SYSREF Input
        2. 9.3.2.2 SNR and Clock Jitter
      3. 9.3.3 Digital Output Interface
        1. 9.3.3.1 One-Wire Interface: 14x Serialization
        2. 9.3.3.2 Two-Wire Interface: 7x Serialization
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Clock Divider
      2. 9.4.2 Chopper Functionality
      3. 9.4.3 Power-Down Control
      4. 9.4.4 Internal Dither Algorithm
      5. 9.4.5 Summary of Performance Mode Registers
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
          1. 9.5.1.1.1 Serial Register Write
          2. 9.5.1.1.2 Serial Register Readout
      2. 9.5.2 ADC3441 Power-Up Requirements
    6. 9.6 Register Maps
      1. 9.6.1 Serial Register Description
        1. 9.6.1.1  Register 01h (address = 01h)
        2. 9.6.1.2  Register 03h (address = 03h)
        3. 9.6.1.3  Register 04h (address = 04h)
        4. 9.6.1.4  Register 05h (address = 05h)
        5. 9.6.1.5  Register 06h (address = 06h)
        6. 9.6.1.6  Register 07h (address = 07h)
        7. 9.6.1.7  Register 09h (address = 09h)
        8. 9.6.1.8  Register 0Ah (address = 0Ah)
        9. 9.6.1.9  Register 0Bh (address = 0Bh)
        10. 9.6.1.10 Register 13h (address = 13h)
        11. 9.6.1.11 Register 0Eh (address = 0Eh)
        12. 9.6.1.12 Register 0Fh (address = 0Fh)
        13. 9.6.1.13 Register 15h (address = 15h)
        14. 9.6.1.14 Register 25h (address = 25h)
        15. 9.6.1.15 Register 27h (address = 27h)
        16. 9.6.1.16 Register 11Dh (address = 11Dh)
        17. 9.6.1.17 Register 122h (address = 122h)
        18. 9.6.1.18 Register 134h (address = 134h)
        19. 9.6.1.19 Register 139h (address = 139h)
        20. 9.6.1.20 Register 21Dh (address = 21Dh)
        21. 9.6.1.21 Register 222h (address = 222h)
        22. 9.6.1.22 Register 234h (address = 234h)
        23. 9.6.1.23 Register 239h (address = 239h)
        24. 9.6.1.24 Register 308h (address = 308h)
        25. 9.6.1.25 Register 41Dh (address = 41Dh)
        26. 9.6.1.26 Register 422h (address = 422h)
        27. 9.6.1.27 Register 434h (address = 434h)
        28. 9.6.1.28 Register 439h (address = 439h)
        29. 9.6.1.29 Register 51Dh (address = 51Dh)
        30. 9.6.1.30 Register 522h (address = 522h)
        31. 9.6.1.31 Register 534h (address = 534h)
        32. 9.6.1.32 Register 539h (address = 539h)
        33. 9.6.1.33 Register 608h (address = 608h)
        34. 9.6.1.34 Register 70Ah (address = 70Ah)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Driving Circuit Design: Low Input Frequencies
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 相关链接
    2. 13.2 接收文档更新通知
    3. 13.3 社区资源
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Analog supply voltage range, AVDD –0.3 2.1 V
Digital supply voltage range, DVDD –0.3 2.1 V
Voltage applied to
input pins		 INAP, INBP, INAM, INBM –0.3 min (1.9, AVDD + 0.3) V
CLKP, CLKM –0.3 AVDD + 0.3
SYSREFP, SYSREFM –0.3 AVDD + 0.3
SCLK, SEN, SDATA, RESET, PDN –0.3 3.9
Temperature Operating free-air, TA –40 85 ºC
Operating junction, TJ 125
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(3)
MIN NOM MAX UNIT
SUPPLIES
AVDD Analog supply voltage range 1.7 1.8 1.9 V
DVDD Digital supply voltage range 1.7 1.8 1.9 V
ANALOG INPUT
VID Differential input voltage For input frequencies < 450 MHz 2 VPP
For input frequencies < 600 MHz 1
VIC Input common-mode voltage VCM ± 0.025 V
CLOCK INPUT
Input clock frequency Sampling clock frequency 15(2) 125(1) MSPS
Input clock amplitude (differential) Sine wave, ac-coupled 0.2 1.5 VPP
LPECL, ac-coupled 1.6
LVDS, ac-coupled 0.7
Input clock duty cycle 35% 50% 65%
Input clock common-mode voltage 0.95 V
DIGITAL OUTPUTS
CLOAD External load capacitance from each output pin to GND 3.3 pF
RLOAD Differential load resistance to be placed across the positive and negative pins of the LVDS output pair 100 Ω
(1) With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 500 MSPS.
(2) See Table 3 for details.
(3) After power-up, only use the RESET pin to reset the device for the first time; see the Register Initialization section for details.

7.4 Thermal Information

THERMAL METRIC(1) ADC344x UNIT
RTQ (VQFN)
56 PINS
RθJA Junction-to-ambient thermal resistance 25.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 9.5 °C/W
RθJB Junction-to-board thermal resistance 3.4 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 3.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics: General

at maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted); typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Differential input full-scale 2.0 VPP
ri Input resistance Differential at dc 6.6 kΩ
ci Input capacitance Differential at dc 3.7 pF
VOC(VCM) VCM common-mode voltage output 0.8 0.95 1.1 V
VCM output current capability 10 mA
Input common-mode current Per analog input pin 1.5 µA/MSPS
Analog input bandwidth
(–3-dB point)		 50-Ω differential source driving 50-Ω termination across INP and INM 540 MHz
DC ACCURACY
EO Offset error –25 25 mV
αEO Temperature coefficient of offset error ±0.024 mV/°C
EG Overall dc gain error of a channel ADC3441 –2 2 %FS
ADC3442, ADC3443, ADC3444 -2.5 2.5
αEG Temperature coefficient of overall gain error 0.005 Δ%FS/°C
CHANNEL-TO-CHANNEL ISOLATION
Crosstalk(1)(2) fIN = 10 MHz Between near channels 105 dB
Between far channels 105
fIN = 100 MHz Between near channels 95
Between far channels 105
fIN = 200 MHz Between near channels 94
Between far channels 105
fIN = 230 MHz Between near channels 92
Between far channels 105
fIN = 300 MHz Between near channels 85
Between far channels 105
(1) Crosstalk is measured with a –1-dBFS input signal on the aggressor channel and no input on the victim channel.
(2) Channels A and B are near to each other but far from channels C and D. Similarly, channels C and D are near to each other but far from channels A and B; see the Pin Configuration and Functions section for more information.

7.6 Electrical Characteristics: ADC3441, ADC3442

at maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted); typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C
PARAMETER ADC3441 ADC3442 UNIT
MIN TYP MAX MIN TYP MAX
ADC clock frequency 25 50 MSPS
Resolution 14 14 Bits
1.8-V analog supply current 54 74 71 97 mA
1.8-V digital supply current 45 67 56 83 mA
Total power dissipation 177 215 228 277 mW
Global power-down dissipation 5 17 5 17 mW
Standby power-down dissipation 34 103 35 103 mW

7.7 Electrical Characteristics: ADC3443, ADC3444

at maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted); typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C
PARAMETER ADC3443 ADC3444 UNIT
MIN TYP MAX MIN TYP MAX
ADC clock frequency 80 125 MSPS
Resolution 14 14 Bits
1.8-V analog supply current 92 125 119 162 mA
1.8-V digital supply current 68 101 98 145 mA
Total power dissipation 288 350 391 475 mW
Global power-down dissipation 5 17 5 17 mW
Standby power-down dissipation 40 103 43 103 mW

7.8 AC Performance: ADC3441

at maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted); typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C
PARAMETER TEST CONDITIONS ADC3441 (fS = 25 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
SNR Signal-to-noise ratio
(from 1-MHz offset)		 fIN = 10 MHz 73.1 73.5 dBFS
fIN = 20 MHz 70.9 72.9 73.4
fIN = 70 MHz 72.5 73
fIN = 100 MHz 72.4 72.7
fIN = 170 MHz 71.4 71.7
fIN = 230 MHz 70.3 70.5
Signal-to-noise ratio
(full Nyquist band)		 fIN = 10 MHz 72.4 72.9
fIN = 20 MHz 72.2 72.7
fIN = 70 MHz 71.9 72.4
fIN = 100 MHz 71.7 72.0
fIN = 170 MHz 70.9 71.1
fIN = 230 MHz 69.7 69.9
NSD(1) Noise spectral density (averaged across Nyquist zone) fIN = 10 MHz –143.7 –144.1 dBFS/Hz
fIN = 20 MHz –143.5 –141.5 –143.9
fIN = 70 MHz –143.1 –143.6
fIN = 100 MHz –143.0 –143.3
fIN = 170 MHz –142.0 –142.3
fIN = 230 MHz –140.9 –141.1
SINAD(1) Signal-to-noise and distortion ratio fIN = 10 MHz 73.1 73.4 dBFS
fIN = 20 MHz 69.9 72.9 73.2
fIN = 70 MHz 71.7 71.9
fIN = 100 MHz 72.6 72.8
fIN = 170 MHz 71.2 71.4
fIN = 230 MHz 69.9 70.1
ENOB(1) Effective number of bits fIN = 10 MHz 11.9 11.9 Bits
fIN = 20 MHz 11.3 11.8 11.8
fIN = 70 MHz 11.7 11.8
fIN = 100 MHz 11.8 11.8
fIN = 170 MHz 11.5 11.6
fIN = 230 MHz 11.3 11.4
SFDR Spurious-free dynamic range fIN = 10 MHz 91 89 dBc
fIN = 20 MHz 82 91 85
fIN = 70 MHz 92 87
fIN = 100 MHz 85 82
fIN = 170 MHz 86 85
fIN = 230 MHz 81 81
HD2 Second-order harmonic distortion fIN = 10 MHz 92 93 dBc
fIN = 20 MHz 82 92 91
fIN = 70 MHz 92 91
fIN = 100 MHz 96 94
fIN = 170 MHz 86 85
fIN = 230 MHz 84 84
HD3 Third-order harmonic distortion fIN = 10 MHz 96 90 dBc
fIN = 20 MHz 82 93 89
fIN = 70 MHz 93 88
fIN = 100 MHz 85 82
fIN = 170 MHz 89 89
fIN = 230 MHz 82 82
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 100 93 dBc
fIN = 20 MHz 87 97 92
fIN = 70 MHz 97 92
fIN = 100 MHz 97 94
fIN = 170 MHz 92 90
fIN = 230 MHz 98 92
THD Total harmonic distortion fIN = 10 MHz 90 86 dBc
fIN = 20 MHz 79 90 85
fIN = 70 MHz 90 85
fIN = 100 MHz 84 80
fIN = 170 MHz 84 83
fIN = 230 MHz 80 80
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz,
each tone at –7 dBFS		 –97 –97 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz,
each tone at –7 dBFS		 –88 –88
INL Integral nonlinearity fIN = 20 MHz ±0.75 ±3 ±0.75 LSBs
DNL Differential nonlinearity fIN = 20 MHz –0.95 ±0.6 ±0.6 LSBs
(1) Reported from a 1-MHz offset.

7.9 AC Performance: ADC3442

at maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted); typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C
PARAMETER TEST CONDITIONS ADC3442 (fS = 50 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
SNR Signal-to-noise ratio
(from 1-MHz offset)		 fIN = 10 MHz 73.1 73.5 dBFS
fIN = 20 MHz 70.7 72.9 73.3
fIN = 70 MHz 72.7 73.1
fIN = 100 MHz 71.9 72.6
fIN = 170 MHz 71.5 71.8
fIN = 230 MHz 70.4 70.8
Signal-to-noise ratio
(full Nyquist band)		 fIN = 10 MHz 72.5 72.9
fIN = 20 MHz 72.3 72.7
fIN = 70 MHz 71.9 72.3
fIN = 100 MHz 71.3 72.1
fIN = 170 MHz 71.0 71.2
fIN = 230 MHz 69.8 70.2
NSD(1) Noise spectral density (averaged across Nyquist zone) fIN = 10 MHz –146.9 –147.3 dBFS/Hz
fIN = 20 MHz –146.7 –144.5 –146.9
fIN = 70 MHz –146.5 –146.9
fIN = 100 MHz –145.7 –146.4
fIN = 170 MHz –145.3 –145.6
fIN = 230 MHz –144.2 –144.6
SINAD(1) Signal-to-noise and distortion ratio fIN = 10 MHz 73 73.4 dBFS
fIN = 20 MHz 69.7 72.2 72.7
fIN = 70 MHz 72.2 72.7
fIN = 100 MHz 72.1 73.2
fIN = 170 MHz 71.4 71.8
fIN = 230 MHz 69.8 70.1
ENOB(1) Effective number of bits fIN = 10 MHz 11.9 11.9 Bits
fIN = 20 MHz 11.3 11.8 11.8
fIN = 70 MHz 11.8 11.8
fIN = 100 MHz 11.7 11.9
fIN = 170 MHz 11.6 11.6
fIN = 230 MHz 11.4 11.4
SFDR Spurious-free dynamic range fIN = 10 MHz 90 90 dBc
fIN = 20 MHz 82 92 90
fIN = 70 MHz 92 90
fIN = 100 MHz 87 87
fIN = 170 MHz 86 84
fIN = 230 MHz 83 82
HD2 Second-order harmonic distortion fIN = 10 MHz 95 92 dBc
fIN = 20 MHz 83 99 94
fIN = 70 MHz 93 91
fIN = 100 MHz 92 92
fIN = 170 MHz 87 85
fIN = 230 MHz 85 83
HD3 Third-order harmonic distortion fIN = 10 MHz 90 92 dBc
fIN = 20 MHz 82 94 91
fIN = 70 MHz 94 91
fIN = 100 MHz 87 87
fIN = 170 MHz 88 89
fIN = 230 MHz 83 88
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 99 95 dBc
fIN = 20 MHz 87 99 93
fIN = 70 MHz 99 93
fIN = 100 MHz 92 94
fIN = 170 MHz 97 89
fIN = 230 MHz 97 91
THD Total harmonic distortion fIN = 10 MHz 89 87 dBc
fIN = 20 MHz 79 90 87
fIN = 70 MHz 90 87
fIN = 100 MHz 86 85
fIN = 170 MHz 85 83
fIN = 230 MHz 81 81
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 –92 –92 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 –87 –87
INL Integral nonlinearity fIN = 20 MHz ±0.8 ±3 ±0.8 LSBs
DNL Differential nonlinearity fIN = 20 MHz –0.95 ±0.6 ±0.6 LSBs
(1) Reported from a 1-MHz offset.

7.10 AC Performance: ADC3443

at maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted); typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C
PARAMETER TEST CONDITIONS ADC3443 (fS = 80 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
SNR Signal-to-noise ratio
(from 1-MHz offset)		 fIN = 10 MHz 72.9 73.2 dBFS
fIN = 70 MHz 70.7 72.8 73.1
fIN = 100 MHz 72.5 72.9
fIN = 170 MHz 72.1 72.4
fIN = 230 MHz 71.4 71.7
Signal-to-noise ratio
(full Nyquist band)		 fIN = 10 MHz 72.5 72.8
fIN = 70 MHz 72.4 72.8
fIN = 100 MHz 72.1 72.6
fIN = 170 MHz 71.7 72.0
fIN = 230 MHz 71.1 71.4
NSD(1) Noise spectral density (averaged across Nyquist zone) fIN = 10 MHz –148.8 –149.1 dBFS/Hz
fIN = 70 MHz –148.7 –146.6 –149.0
fIN = 100 MHz –148.4 –148.8
fIN = 170 MHz –148.0 –148.3
fIN = 230 MHz –147.3 –147.6
SINAD(1) Signal-to-noise and distortion ratio fIN = 10 MHz 72.8 73.2 dBFS
fIN = 70 MHz 69.7 72.2 72.4
fIN = 100 MHz 72.7 73
fIN = 170 MHz 71.9 72.2
fIN = 230 MHz 71.2 71.4
ENOB(1) Effective number of bits fIN = 10 MHz 11.8 11.9 Bits
fIN = 70 MHz 11.3 11.8 11.8
fIN = 100 MHz 11.8 11.8
fIN = 170 MHz 11.7 11.7
fIN = 230 MHz 11.5 11.6
SFDR Spurious-free dynamic range fIN = 10 MHz 89 89 dBc
fIN = 70 MHz 81 90 89
fIN = 100 MHz 92 92
fIN = 170 MHz 88 86
fIN = 230 MHz 86 84
HD2 Second-order harmonic distortion fIN = 10 MHz 94 91 dBc
fIN = 70 MHz 81 96 91
fIN = 100 MHz 97 94
fIN = 170 MHz 88 86
fIN = 230 MHz 87 85
HD3 Third-order harmonic distortion fIN = 10 MHz 89 90 dBc
fIN = 70 MHz 81 91 90
fIN = 100 MHz 94 100
fIN = 170 MHz 95 93
fIN = 230 MHz 87 87
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 100 95 dBc
fIN = 70 MHz 86 98 94
fIN = 100 MHz 95 94
fIN = 170 MHz 95 94
fIN = 230 MHz 94 92
THD Total harmonic distortion fIN = 10 MHz 88 86 dBc
fIN = 70 MHz 78 89 87
fIN = 100 MHz 91 90
fIN = 170 MHz 87 84
fIN = 230 MHz 84 82
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 –98 –98 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 –88 –88
INL Integral nonlinearity fIN = 70 MHz ±0.8 ±3 ±0.8 LSBs
DNL Differential nonlinearity fIN = 70 MHz –0.95 ±0.7 ±0.7 LSBs
(1) Reported from a 1-MHz offset.

7.11 AC Performance: ADC3444

at maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted); typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C
PARAMETER TEST CONDITIONS ADC3444 (fS = 125 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
SNR Signal-to-noise ratio
(from 1-MHz offset)		 fIN = 10 MHz 72.6 73 dBFS
fIN = 70 MHz 70.2 72.5 72.9
fIN = 100 MHz 72.2 72.7
fIN = 170 MHz 71.7 72.3
fIN = 230 MHz 70.8 71.7
Signal-to-noise ratio
(full Nyquist band)		 fIN = 10 MHz 72.4 72.8
fIN = 70 MHz 72.3 72.7
fIN = 100 MHz 72.1 72.5
fIN = 170 MHz 71.5 72.1
fIN = 230 MHz 70.6 71.5
NSD(1) Noise spectral density (averaged across Nyquist zone) fIN = 10 MHz –150.4 –150.9 dBFS/Hz
fIN = 70 MHz –150.4 –148.1 –150.8
fIN = 100 MHz –150.1 –150.5
fIN = 170 MHz –149.5 –150.2
fIN = 230 MHz –148.7 –149.6
SINAD(1) Signal-to-noise and distortion ratio fIN = 10 MHz 72.6 72.9 dBFS
fIN = 70 MHz 69.3 72.3 72.7
fIN = 100 MHz 72.3 72.7
fIN = 170 MHz 71.5 72
fIN = 230 MHz 69.9 70.6
ENOB(1) Effective number of bits fIN = 10 MHz 11.8 11.8 Bits
fIN = 70 MHz 11.2 11.8 11.8
fIN = 100 MHz 11.7 11.8
fIN = 170 MHz 11.6 11.7
fIN = 230 MHz 11.4 11.6
SFDR Spurious-free dynamic range fIN = 10 MHz 92 87 dBc
fIN = 70 MHz 80 93 88
fIN = 100 MHz 89 89
fIN = 170 MHz 86 84
fIN = 230 MHz 82 82
HD2 Second-order harmonic distortion fIN = 10 MHz 93 93 dBc
fIN = 70 MHz 80 94 91
fIN = 100 MHz 90 90
fIN = 170 MHz 86 85
fIN = 230 MHz 81 80
HD3 Third-order harmonic distortion fIN = 10 MHz 96 88 dBc
fIN = 70 MHz 81 95 89
fIN = 100 MHz 95 89
fIN = 170 MHz 93 87
fIN = 230 MHz 87 86
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 100 93 dBc
fIN = 70 MHz 86 99 94
fIN = 100 MHz 94 92
fIN = 170 MHz 96 93
fIN = 230 MHz 94 90
THD Total harmonic distortion fIN = 10 MHz 91 85 dBc
fIN = 70 MHz 77 91 85
fIN = 100 MHz 88 86
fIN = 170 MHz 85 82
fIN = 230 MHz 80 78
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 –97 –97 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 –87 –87
INL Integral nonlinearity fIN = 70 MHz ±0.75 ±3 ±0.75 LSBs
DNL Differential nonlinearity fIN = 70 MHz –0.95 ±0.7 ±0.7 LSBs
(1) Reported from a 1-MHz offset.

7.12 Digital Characteristics

the dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1; AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, PDN)
VIH High-level input voltage All digital inputs support 1.8-V and 3.3-V CMOS logic levels 1.3 V
VIL Low-level input voltage 0.4 V
IIH High-level input current RESET, SDATA, SCLK, PDN VHIGH = 1.8 V 10 µA
SEN(1) VHIGH = 1.8 V 0
IIL Low-level input current RESET, SDATA, SCLK, PDN VLOW = 0 V 0 µA
SEN VLOW = 0 V 10
DIGITAL INPUTS (SYSREFP, SYSREFM)
Differential swing 0.2 0.8 1.0 V
Common-mode voltage for SYSREF(2) 0.9 V
DIGITAL OUTPUTS (CMOS Interface, SDOUT)
VOH High-level output voltage DVDD – 0.1 DVDD V
VOL Low-level output voltage 0 0.1 V
DIGITAL OUTPUTS (LVDS Interface)
VODH High-level output differential voltage With an external 100-Ω termination 280 350 –280 mV
VODL Low-level output differential voltage With an external 100-Ω termination –460 –350 –460 mV
VOCM Output common-mode voltage 0.9 1.05 1.2 V
(1) SEN has an internal 150-kΩ pullup resistor to AVDD. SPI pins (SEN, SCLK, SDATA) may be driven by 1.8 V or 3.3 V CMOS buffers.
(2) SYSREF is internally biased to 0.9 V.

7.13 Timing Requirements: General

typical values are at TA = 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted); minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C
MIN TYP MAX UNIT
tA Aperture delay 1.24 1.44 1.64 ns
Aperture delay matching between two channels of the same device ±70 ps
Variation of aperture delay between two devices at the same temperature and supply voltage ±150 ps
tJ Aperture jitter 130 fS rms
Wake-up time Time to valid data after exiting standby power-down mode 35 200 µs
Time to valid data after exiting global power-down mode (in this mode, both channels power down) 85 450 µs
ADC latency(6) 2-wire mode (default) 9 Clock cycles
1-wire mode 8 Clock cycles
tSU_SYSREF SYSREF reference time Setup time for SYSREF referenced to input clock falling edge 1000 ps
tH_SYSREF Hold time for SYSREF referenced to input clock falling edge 100 ps

7.14 Timing Requirements: LVDS Output

typical values are at 25°C, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 7x serialization (2-wire mode), CLOAD = 3.3 pF(2), and RLOAD = 100 Ω(3) (unless otherwise noted); minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C(4)(1)
MIN TYP MAX UNIT
tSU Data setup time: data valid to zero-crossing of differential output clock
(CLKOUTP – CLKOUTM)(5)		 0.36 0.42 ns
tHO Data hold time: zero-crossing of differential output clock (CLKOUTP – CLKOUTM) to data becoming invalid(5) 0.36 0.47 ns
LVDS bit clock duty cycle: duty cycle of differential clock (CLKOUTP – CLKOUTM) 49%
tPDI Clock propagation delay: input clock falling edge cross-over to frame clock rising edge cross-over 15 MSPS < sampling frequency <
125 MSPS		 1-wire mode 2.7 4.5 6.5 ns
2-wire mode 0.44 × tS + tDELAY ns
tDELAY Delay time 3 4.5 5.9 ns
tFALL,
tRISE		 Data fall time, data rise time: rise time measured from –100 mV to 100 mV,
15 MSPS ≤ Sampling frequency ≤ 125 MSPS		 0.11 ns
tCLKRISE,
tCLKFALL		 Output clock rise time, output clock fall time: rise time measured from –100 mV to 100 mV,
15 MSPS ≤ Sampling frequency ≤ 125 MSPS		 0.11 ns
(1) Timing parameters are ensured by design and characterization and are not tested in production.
(2) CLOAD is the effective external single-ended load capacitance between each output pin and ground
(3) RLOAD is the differential load resistance between the LVDS output pair.
(4) Measurements are done with a transmission line of a 100-Ω characteristic impedance between the device and load. Setup and hold time specifications take into account the effect of jitter on the output data and clock.
(5) Data valid refers to a logic high of +100 mV and a logic low of –100 mV.
(6) Overall latency = ADC latency + tPDI; see Figure 141.

Table 1. LVDS Timings at Lower Sampling Frequencies: 7x Serialization (2-Wire Mode)

SAMPLING FREQUENCY (MSPS) SETUP TIME
(tSU, ns)		 HOLD TIME
(tHO, ns)
MIN TYP MAX MIN TYP MAX
25 2.27 2.6 2.41 2.6
40 1.44 1.6 1.51 1.7
50 1.2 1.32 1.24 1.4
60 0.95 1.04 0.97 1.09
80 0.68 0.75 0.72 0.81
100 0.5 0.57 0.53 0.62

Table 2. LVDS Timings at Lower Sampling Frequencies: 14x Serialization (1-Wire Mode)

SAMPLING FREQUENCY (MSPS) SETUP TIME
(tSU, ns)		 HOLD TIME
(tHO, ns)
MIN TYP MAX MIN TYP MAX
25 1.1 1.24 1.19 1.34
40 0.66 0.72 0.74 0.82
50 0.48 0.55 0.54 0.64
60 0.35 0.41 0.42 0.51
80 0.17 0.24 0.3 0.38

7.15 Typical Characteristics: ADC3441

typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, and dither on (unless otherwise noted)
ADC3441 ADC3442 ADC3443 ADC3444 D701_SBAS670.gif
SFDR = 98 dBc, SNR = 73.1 dBFS, SINAD = 73 dBFS,
THD = 97 dBc, HD2 = 110.0 dBc,
HD3 = 98 dBc, SFDR = 100 dBc (excluding HD2, HD3)
Figure 1. FFT for 10-MHz Input Signal (Dither On)
ADC3441 ADC3442 ADC3443 ADC3444 D703_SBAS670.gif
SFDR = 92 dBc, SNR = 72.5 dBFS, SINAD = 72.3 dBFS,
THD = 91 dBc, HD2 = 108 dBc,
HD3 = 92 dBc, SFDR = 101 dBc (excluding HD2, HD3)
Figure 3. FFT for 70-MHz Input Signal (Dither On)
ADC3441 ADC3442 ADC3443 ADC3444 D705_SBAS670.gif
SFDR = 87 dBc, SNR = 71.5 dBFS, SINAD = 71.1 dBFS,
THD = 85 dBc, HD2 = 90 dBc,
HD3 = 87 dBc, SFDR = 100 dBc (excluding HD2, HD3)
Figure 5. FFT for 170-MHz Input Signal (Dither On)
ADC3441 ADC3442 ADC3443 ADC3444 D707_SBAS670.gif
SFDR = 76 dBc, SNR = 69.4 dBFS, SINAD = 68.8 dBFS,
THD = 75 dBc, HD2 = 76 dBc,
HD3 = 83 dBc, SFDR = 96 dBc (excluding HD2, HD3)
Figure 7. FFT for 270-MHz Input Signal (Dither On)
ADC3441 ADC3442 ADC3443 ADC3444 D709_SBAS670.gif
SFDR = 68 dBc, SNR = 66.7 dBFS, SINAD = 66.5 dBFS,
THD = 92 dBc, HD2 = 68 dBc,
HD3 = 90 dBc, SFDR = 91 dBc (excluding HD2, HD3)
Figure 9. FFT for 450-MHz Input Signal (Dither On)
ADC3441 ADC3442 ADC3443 ADC3444 D711_SBAS670.gif
fIN1 = 46.3 MHz, fIN2 = 50.3 MHz, IMD3 = 86 dBFS,
each tone at –7 dBFS
Figure 11. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D713_SBAS670.gif
fIN1 = 184.5 MHz, fIN2 = 189.5 MHz, IMD3 = 93 dBFS,
each tone at –7 dBFS
Figure 13. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D715_SBAS670.gif
Figure 15. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D717_SBAS670.gif
Figure 17. Signal-to-Noise Ratio vs Input Frequency
ADC3441 ADC3442 ADC3443 ADC3444 D719_SBAS670.gif
Figure 19. Performance vs Input Amplitude (30 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D721_SBAS670.gif
Figure 21. Performance vs Input Common-Mode Voltage
(30 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D723_SBAS670.gif
Figure 23. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (30 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D725_SBAS670.gif
Figure 25. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature (30 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D727_SBAS670.gif
Figure 27. Performance vs Clock Amplitude (40 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D729_SBAS670.gif
Figure 29. Performance vs Clock Duty Cycle (30 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D731_SBAS670.gif
RMS Noise = 1.33 LSBs
Figure 31. Idle Channel Histogram
ADC3441 ADC3442 ADC3443 ADC3444 D902_SBAS670.gif
Figure 33. Differential Nonlinearity for 20-MHz Input
ADC3441 ADC3442 ADC3443 ADC3444 D702_SBAS670.gif
SFDR = 90 dBc, SNR = 73.5 dBFS, SINAD = 73.2 dBFS,
THD = 88 dBc, HD2 = 90 dBc,
HD3 = 100 dBc, SFDR = 92 dBc (excluding HD2, HD3)
Figure 2. FFT for 10-MHz Input Signal (Dither Off)
ADC3441 ADC3442 ADC3443 ADC3444 D704_SBAS670.gif
SFDR = 90 dBc, SNR = 72.9 dBFS, SINAD = 72.7 dBFS,
THD = 89 dBc, HD2 = 90 dBc,
HD3 = 101 dBc, SFDR = 93 dBc (excluding HD2, HD3)
Figure 4. FFT for 70-MHz Input Signal (Dither Off)
ADC3441 ADC3442 ADC3443 ADC3444 D706_SBAS670.gif
SFDR = 88 dBc, SNR = 71.7 dBFS, SINAD = 71.4 dBFS,
THD = 85 dBc, HD2 = 88 dBc,
HD3 = 91 dBc, SFDR = 93 dBc (excluding HD2, HD3)
Figure 6. FFT for 170-MHz Input Signal (Dither Off)
ADC3441 ADC3442 ADC3443 ADC3444 D708_SBAS670.gif
SFDR = 75 dBc, SNR = 69.6 dBFS, SINAD = 68.6 dBFS,
THD = 74 dBc, HD2 = 75 dBc,
HD3 = 80 dBc, SFDR = 91 dBc (excluding HD2, HD3)
Figure 8. FFT for 270-MHz Input Signal (Dither Off)
ADC3441 ADC3442 ADC3443 ADC3444 D710_SBAS670.gif
SFDR = 66 dBc, SNR = 66.8 dBFS, SINAD = 66.5 dBFS,
THD = 88 dBc, HD2 = 66 dBc,
HD3 = 97 dBc, SFDR = 90 dBc (excluding HD2, HD3)
Figure 10. FFT for 450-MHz Input Signal (Dither Off)
ADC3441 ADC3442 ADC3443 ADC3444 D712_SBAS670.gif
fIN1 = 46.3 MHz, fIN2 = 50.3 MHz, IMD3 = 105 dBFS,
each tone at –36 dBFS
Figure 12. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D714_SBAS670.gif
fIN1 = 184.5 MHz, fIN2 = 189.5 MHz, IMD3 = 109 dBFS,
each tone at –36 dBFS
Figure 14. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D716_SBAS670.gif
Figure 16. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D718_SBAS670.gif
Figure 18. Spurious-Free Dynamic Range vs
Input Frequency
ADC3441 ADC3442 ADC3443 ADC3444 D720_SBAS670.gif
Figure 20. Performance vs Input Amplitude (170 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D722_SBAS670.gif
Figure 22. Performance vs Input Common-Mode Voltage (170 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D724_SBAS670.gif
Figure 24. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (30 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D726_SBAS670.gif
Figure 26. Signal-to-Noise Ratio vs
DVDD Supply and Temperature (30 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D728_SBAS670.gif
Figure 28. Performance vs Clock Amplitude (150 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D730_SBAS670.gif
Figure 30. Performance vs Clock Duty Cycle (150 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D901_SBAS670.gif
Figure 32. Integral Nonlinearity for 20-MHz Input

7.16 Typical Characteristics: ADC3442

typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, and dither on (unless otherwise noted)
ADC3441 ADC3442 ADC3443 ADC3444 D501_SBAS670.gif
SFDR = 89 dBc, SNR = 73.1 dBFS, SINAD = 73 dBFS,
THD = 89 dBc, HD2 = 111 dBc,
HD3 = 89 dBc, SFDR = 100 dBc (excluding HD2, HD3)
Figure 34. FFT for 10-MHz Input Signal
(Chopper On, Dither On)
ADC3441 ADC3442 ADC3443 ADC3444 D503_SBAS670.gif
SFDR = 86 dBc, SNR = 72.7 dBFS, SINAD = 72.5 dBFS,
THD = 85 dBc, HD2 = 92 dBc,
HD3 = 86 dBc, SFDR = 100 dBc (excluding HD2, HD3)
Figure 36. FFT for 70-MHz Input Signal (Dither On)
ADC3441 ADC3442 ADC3443 ADC3444 D505_SBAS670.gif
SFDR = 86 dBc, SNR = 71.6 dBFS, SINAD = 71.4 dBFS,
THD = 85 dBc, HD2 = 92 dBc,
HD3 = 86 dBc, SFDR = 99 dBc (excluding HD2, HD3)
Figure 38. FFT for 170-MHz Input Signal (Dither On)
ADC3441 ADC3442 ADC3443 ADC3444 D507_SBAS670.gif
SFDR = 75 dBc, SNR = 70.3 dBFS, SINAD = 69.1 dBFS,
THD = 74 dBc, HD2 = -75 dBc,
HD3 = 81 dBc, SFDR = 95 dBc (excluding HD2, HD3)
Figure 40. FFT for 270-MHz Input Signal (Dither On)
ADC3441 ADC3442 ADC3443 ADC3444 D509_SBAS670.gif
SFDR = 68 dBc, SNR = 68.2 dBFS, SINAD = 68 dBFS,
THD = 86 dBc, HD2 = 68 dBc, HD3 = 87 dBc
Figure 42. FFT for 450-MHz Input Signal (Dither On)
ADC3441 ADC3442 ADC3443 ADC3444 D511_SBAS670.gif
fIN1 = 46.3 MHz, fIN2 = 50.3 MHz, IMD3 = 102 dBFS,
each tone at –7 dBFS
Figure 44. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D513_SBAS670.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 93 dBFS,
each tone at –7 dBFS
Figure 46. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D515_SBAS670.gif
Figure 48. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D517_SBAS670.gif
Figure 50. Signal-to-Noise Ratio vs Input Frequency
ADC3441 ADC3442 ADC3443 ADC3444 D519_SBAS670.gif
Figure 52. Performance vs Input Amplitude (30 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D521_SBAS670.gif
Figure 54. Performance vs Input Common-Mode Voltage
(30 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D523_SBAS670.gif
Figure 56. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (30 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D525_SBAS670.gif
Figure 58. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature (30 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D527_SBAS670.gif
Figure 60. Performance vs Clock Amplitude (40 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D529_SBAS670.gif
Figure 62. Performance vs Clock Duty Cycle (30 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D531_SBAS670.gif
RMS noise = 1.3 LSBs
Figure 64. Idle Channel Histogram
ADC3441 ADC3442 ADC3443 ADC3444 D904_SBAS670.gif
Figure 66. Differential Nonlinearity for 20-MHz Input
ADC3441 ADC3442 ADC3443 ADC3444 D502_SBAS670.gif
SFDR = 85 dBc, SNR = 73.5 dBFS, SINAD = 73.3 dBFS,
THD = 84 dBc, HD2 = 92 dBc,
HD3 = 85 dBc, SFDR = 96 dBc (excluding HD2, HD3)
Figure 35. FFT for 10-MHz Input Signal
(Chopper On, Dither Off)
ADC3441 ADC3442 ADC3443 ADC3444 D504_SBAS670.gif
SFDR = 90 dBc, SNR = 73.1 dBFS, SINAD = 73 dBFS,
THD = 88 dBc, HD2 = 92 dBc,
HD3 = 90 dBc, SFDR = 95 dBc (excluding HD2, HD3)
Figure 37. FFT for 70-MHz Input Signal (Dither Off)
ADC3441 ADC3442 ADC3443 ADC3444 D506_SBAS670.gif
SFDR = 90 dBc, SNR = 71.8 dBFS, SINAD = 71.6 dBFS,
THD = 87 dBc, HD2 = 90 dBc,
HD3 = 108 dBc, SFDR = 93 dBc (excluding HD2, HD3)
Figure 39. FFT for 170-MHz Input Signal (Dither Off)
ADC3441 ADC3442 ADC3443 ADC3444 D508_SBAS670.gif
SFDR = 75 dBc, SNR = 70.6 dBFS, SINAD = 69.6 dBFS,
THD = 73 dBc, HD2 = 75 dBc,
HD3 = 78 dBc, SFDR = 91 dBc (excluding HD2, HD3)
Figure 41. FFT for 270-MHz Input Signal (Dither Off)
ADC3441 ADC3442 ADC3443 ADC3444 D510_SBAS670.gif
SFDR = 68 dBc, SNR = 68.5 dBFS, SINAD = 68.3 dBFS,
THD = 86 dBc, HD2 = 68 dBc, HD3 = 90 dBc
Figure 43. FFT for 450-MHz Input Signal (Dither Off)
ADC3441 ADC3442 ADC3443 ADC3444 D512_SBAS670.gif
fIN1 = 46.3 MHz, fIN2 = 50.3 MHz, IMD3 = 110 dBFS,
each tone at –36 dBFS
Figure 45. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D514_SBAS670.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 105 dBFS,
each tone at –36 dBFS
Figure 47. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D516_SBAS670.gif
Figure 49. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D518_SBAS670.gif
Figure 51. Spurious-Free Dynamic Range vs
Input Frequency
ADC3441 ADC3442 ADC3443 ADC3444 D520_SBAS670.gif
Figure 53. Performance vs Input Amplitude (170 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D522_SBAS670.gif
Figure 55. Performance vs Input Common-Mode Voltage (170 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D524_SBAS670.gif
Figure 57. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (30 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D526_SBAS670.gif
Figure 59. Signal-to-Noise Ratio vs
DVDD Supply and Temperature (30 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D528_SBAS670.gif
Figure 61. Performance vs Clock Amplitude (150 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D530_SBAS670.gif
Figure 63. Performance vs Clock Duty Cycle (150 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D903_SBAS670.gif
Figure 65. Integral Nonlinearity for 20-MHz Input

7.17 Typical Characteristics: ADC3443

typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, and dither on (unless otherwise noted)
ADC3441 ADC3442 ADC3443 ADC3444 D301_SBAS670.gif
SFDR = 89 dBc, SNR = 73.1 dBFS, SINAD = 73 dBFS,
THD = 89 dBc, HD2 = 110 dBc, HD3 = 89 dBc
Figure 67. FFT for 10-MHz Input Signal
(Chopper On, Dither On)
ADC3441 ADC3442 ADC3443 ADC3444 D303_SBAS670.gif
SFDR = 91 dBc, SNR = 72.9 dBFS, SINAD = 72.8 dBFS,
THD = 91 dBc, HD2 = 110 dBc, HD3 = 91 dBc
Figure 69. FFT for 70-MHz Input Signal (Dither On)
ADC3441 ADC3442 ADC3443 ADC3444 D305_SBAS670.gif
SFDR = 95 dBc, SNR = 72.1 dBFS, SINAD = 71.9 dBFS,
THD = 93 dBc, HD2 = 106 dBc, HD3 = 95 dBc
Figure 71. FFT for 170-MHz Input Signal (Dither On)
ADC3441 ADC3442 ADC3443 ADC3444 D307_SBAS670.gif
SFDR = 75 dBc, SNR = 70.5 dBFS, SINAD = 69.6 dBFS,
THD = 74 dBc, HD2 = 75 dBc, HD3 = 81 dBc
Figure 73. FFT for 270-MHz Input Signal (Dither On)
ADC3441 ADC3442 ADC3443 ADC3444 D309_SBAS670.gif
SFDR = 66 dBc, SNR = 68.4 dBFS, SINAD = 64.6 dBFS,
THD = 66 dBc, HD2 = 66 dBc, HD3 = 89 dBc
Figure 75. FFT for 450-MHz Input Signal (Dither On)
ADC3441 ADC3442 ADC3443 ADC3444 D311_SBAS670.gif
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 99 dBFS,
each tone at –7 dBFS
Figure 77. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D313_SBAS670.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 90 dBFS,
each tone at –7 dBFS
Figure 79. FFT FOR Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D315_SBAS670.gif
Figure 81. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D317_SBAS670.gif
Figure 83. Signal-to-Noise Ratio vs Input Frequency
ADC3441 ADC3442 ADC3443 ADC3444 D319_SBAS670.gif
Figure 85. Performance vs Input Amplitude (30 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D321_SBAS670.gif
Figure 87. Performance vs Input Common-Mode Voltage
(30 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D323_SBAS670.gif
Figure 89. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (170 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D325_SBAS670.gif
Figure 91. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature (170 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D327_SBAS670.gif
Figure 93. Performance vs Clock Amplitude (40 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D329_SBAS670.gif
Figure 95. Performance vs Clock Duty cycle (30 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D331_SBAS670.gif
RMS noise = 1.28 LSBs
Figure 97. Idle Channel Histogram
ADC3441 ADC3442 ADC3443 ADC3444 D906_SBAS670.gif
Figure 99. Differential Nonlinearity for 70-MHz Input
ADC3441 ADC3442 ADC3443 ADC3444 D302_SBAS670.gif
SFDR = 84 dBc, SNR = 73.2 dBFS, SINAD = 73.1 dBFS,
THD = 83 dBc, HD2 = 94 dBc, HD3 = 84 dBc
Figure 68. FFT for 10-MHz Input Signal
(Chopper On, Dither Off)
ADC3441 ADC3442 ADC3443 ADC3444 D304_SBAS670.gif
SFDR = 85 dBc, SNR = 73.1 dBFS, SINAD = 72.9 dBFS,
THD = 84 dBc, HD2 = 91 dBc, HD3 = 85 dBc
Figure 70. FFT for 70-MHz Input Signal (Dither Off)
ADC3441 ADC3442 ADC3443 ADC3444 D306_SBAS670.gif
SFDR = 92 dBc, SNR = 72.4 dBFS, SINAD = 72.2 dBFS,
THD = 88 dBc, HD2 = 92 dBc, HD3 = 95 dBc
Figure 72. FFT for 170-MHz Input Signal (Dither Off)
ADC3441 ADC3442 ADC3443 ADC3444 D308_SBAS670.gif
SFDR = 75 dBc, SNR = 71 dBFS, SINAD = 69.7 dBFS,
THD = 74 dBc, HD2 = 75 dBc, HD3 = 81 dBc
Figure 74. FFT for 270-MHz Input Signal (Dither Off)
ADC3441 ADC3442 ADC3443 ADC3444 D310_SBAS670.gif
SFDR = 65 dBc, SNR = 68.7 dBFS, SINAD = 64.4 dBFS,
THD = 65 dBc, HD2 = 65 dBc, HD3 = 82 dBc
Figure 76. FFT for 450-MHz Input Signal (Dither Off)
ADC3441 ADC3442 ADC3443 ADC3444 D312_SBAS670.gif
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 105 dBFS,
each tone at –36 dBFS
Figure 78. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D314_SBAS670.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 106 dBFS,
each tone at –36 dBFS
Figure 80. FFT FOR Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D316_SBAS670.gif
Figure 82. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D318_SBAS670.gif
Figure 84. Spurious-Free Dynamic Range vs
Input Frequency
ADC3441 ADC3442 ADC3443 ADC3444 D320_SBAS670.gif
Figure 86. Performance vs Input Amplitude (170 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D322_SBAS670.gif
Figure 88. Performance vs Input Common-Mode Voltage (170 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D324_SBAS670.gif
Figure 90. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (170 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D326_SBAS670.gif
Figure 92. Signal-to-Noise Ratio vs
DVDD Supply and Temperature (170 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D328_SBAS670.gif
Figure 94. Performance vs Clock Amplitude (150 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D330_SBAS670.gif
Figure 96. Performance vs Clock Duty Cycle (150 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D905_SBAS670.gif
Figure 98. Integral Nonlinearity for 70-MHz Input

7.18 Typical Characteristics: ADC3444

typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, and dither on (unless otherwise noted)
ADC3441 ADC3442 ADC3443 ADC3444 D101_SBAS670.gif
SFDR = 95 dBc, SNR = 72.7 dBFS, SINAD = 72.6 dBFS,
THD = 100 dBc, HD2 = 95 dBc, HD3 = 96 dBc
Figure 100. FFT for 10-MHz Input Signal
(Chopper On, Dither On)
ADC3441 ADC3442 ADC3443 ADC3444 D103_SBAS670.gif
SFDR = 96 dBc, SNR = 72.5 dBFS, SINAD = 72.4 dBFS,
THD = 94 dBc, HD2 = 101 dBc, HD3 = 96 dBc
Figure 102. FFT for 70-MHz Input Signal (Dither On)
ADC3441 ADC3442 ADC3443 ADC3444 D105_SBAS670.gif
SFDR = 86 dBc, SNR = 71.7 dBFS, SINAD = 71.6 dBFS,
THD = 93 dBc, HD2 = 86 dBc, HD3 = 99 dBc
Figure 104. FFT for 170-MHz Input Signal (Dither On)
ADC3441 ADC3442 ADC3443 ADC3444 D107_SBAS670.gif
SFDR = 77 dBc, SNR = 70.4 dBFS, SINAD = 69.6 dBFS,
THD = 75 dBc, HD2 = 77 dBc, HD3 = 81 dBc
Figure 106. FFT for 270-MHz Input Signal (Dither On)
ADC3441 ADC3442 ADC3443 ADC3444 D109_SBAS670.gif
SFDR = 72 dBc, SNR = 68.2 dBFS, SINAD = 67.3 dBFS,
THD = 74 dBc, HD2 = 72 dBc, HD3 = 79 dBc
Figure 108. FFT for 450-MHz Input Signal (Dither On)
ADC3441 ADC3442 ADC3443 ADC3444 D111_SBAS670.gif
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 102 dBFS,
each tone at –7 dBFS
Figure 110. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D113_SBAS670.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 88 dBFS,
each tone at –7 dBFS
Figure 112. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D115_SBAS670.gif
Figure 114. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D117_SBAS670.gif
Figure 116. Signal-to-Noise Ratio vs Input Frequency
ADC3441 ADC3442 ADC3443 ADC3444 D119_SBAS670.gif
Figure 118. Performance vs Input Amplitude (30 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D121_SBAS670.gif
Figure 120. Performance vs Input Common-Mode Voltage (30 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D123_SBAS670.gif
Figure 122. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (170 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D125_SBAS670.gif
Figure 124. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature (170 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D127_SBAS670.gif
Figure 126. Performance vs Clock Amplitude (40 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D129_SBAS670.gif
Figure 128. Performance vs Clock Duty Cycle (30 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D131_SBAS670.gif
RMS noise = 1.4 LSBs
Figure 130. Idle Channel Histogram
ADC3441 ADC3442 ADC3443 ADC3444 D908_SBAS670.gif
Figure 132. Differential Nonlinearity for 70-MHz Input
ADC3441 ADC3442 ADC3443 ADC3444 D102_SBAS670.gif
SFDR = 91.8 dBc, SNR = 73.1 dBFS, SINAD = 73 dBFS,
THD = 87 dBc, HD2 = 94 dBc, HD3 = 92 dBc
Figure 101. FFT for 10-MHz Input Signal
(Chopper On, Dither Off)
ADC3441 ADC3442 ADC3443 ADC3444 D104_SBAS670.gif
SFDR = 91 dBc, SNR = 73 dBFS, SINAD = 72.8 dBFS,
THD = 87 dBc, HD2 = 91 dBc, HD3 = 95 dBc
Figure 103. FFT for 70-MHz Input Signal (Dither Off)
ADC3441 ADC3442 ADC3443 ADC3444 D106_SBAS670.gif
SFDR = 85 dBc, SNR = 72.3 dBFS, SINAD = 72.1 dBFS,
THD = 87 dBc, HD2 = 97 dBc, HD3 = 85 dBc
Figure 105. FFT for 170-MHz Input Signal (Dither Off)
ADC3441 ADC3442 ADC3443 ADC3444 D108_SBAS670.gif
SFDR = 74 dBc, SNR = 71 dBFS, SINAD = 70.1 dBFS,
THD = 75 dBc, HD2 = 76 dBc, HD3 = 82 dBc
Figure 107. FFT for 270-MHz Input Signal (Dither Off)
ADC3441 ADC3442 ADC3443 ADC3444 D110_SBAS670.gif
SFDR = 70 dBc, SNR = 68.9 dBFS, SINAD = 67.6 dBFS,
THD = 73 dBc, HD2 = 77 dBc, HD3 = 70 dBc
Figure 109. FFT for 450-MHz Input Signal (Dither Off)
ADC3441 ADC3442 ADC3443 ADC3444 D112_SBAS670.gif
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 100 dBFS,
each tone at –36 dBFS
Figure 111. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D114_SBAS670.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 104 dBFS,
each tone at –36 dBFS
Figure 113. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D116_SBAS670.gif
Figure 115. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D118_SBAS670.gif
Figure 117. Spurious-Free Dynamic Range vs
Input Frequency
ADC3441 ADC3442 ADC3443 ADC3444 D120_SBAS670.gif
Figure 119. Performance vs Input Amplitude (170 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D122_SBAS670.gif
Figure 121. Performance vs Input Common-Mode Voltage (170 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D124_SBAS670.gif
Figure 123. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (170 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D126_SBAS670.gif
Figure 125. Signal-to-Noise Ratio vs
DVDD Supply and Temperature (170 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D128_SBAS670.gif
Figure 127. Performance vs Clock Amplitude (150 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D130_SBAS670.gif
Figure 129. Performance vs Clock Duty Cycle (150 MHz)
ADC3441 ADC3442 ADC3443 ADC3444 D907_SBAS670.gif
Figure 131. Integral Nonlinearity for 70-MHz Input

7.19 Typical Characteristics: Common

typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, and dither on (unless otherwise noted)
ADC3441 ADC3442 ADC3443 ADC3444 D005_SBAS670.gif
fIN = 30 MHz, AIN = –1 dBFS,
test signal amplitude = 50 mVPP
Figure 133. Power-Supply Rejection Ratio vs
Test Signal Frequency
ADC3441 ADC3442 ADC3443 ADC3444 D007_SBAS670.gif
fIN = 170 MHz, AIN = –1 dBFS,
test signal amplitude = 50 mVPP, input VCM = 0.95 V
Figure 135. Common-Mode Rejection Ratio vs
Test Signal Frequency
ADC3441 ADC3442 ADC3443 ADC3444 D009_SBAS670.gif
Figure 137. Power vs Sampling Frequency
(Two-Wire Mode)
ADC3441 ADC3442 ADC3443 ADC3444 D006_SBAS670.gif
fIN = 30.1 MHz, fPSRR = 3 MHz, APSRR = 50 mVPP,
SINAD = 58.63 dBFS, SFDR = 61.57 dBc
Figure 134. Power-Supply Rejection Ratio Spectrum (Chopper On)
ADC3441 ADC3442 ADC3443 ADC3444 D008_SBAS670.gif
fIN = 170.1 MHz, fCMRR = 5 MHz, ACMRR = 50 mVPP,
SINAD = 69.66 dBFS, SFDR = 75.66 dBc
Figure 136. Common-Mode Rejection Ratio Spectrum
ADC3441 ADC3442 ADC3443 ADC3444 D010_SBAS670.gif
Figure 138. Power vs Sampling Frequency
(One-Wire Mode)

7.20 Typical Characteristics: Contour

typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when is chopper enabled, and dither on (unless otherwise noted)
ADC3441 ADC3442 ADC3443 ADC3444 SFDR_SBAS670.png Figure 139. Spurious-Free Dynamic Range (SFDR)
ADC3441 ADC3442 ADC3443 ADC3444 SNR_SBAS670.png Figure 140. Signal-to-Noise Ratio (SNR)
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