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ZHCSDC0A May 2014 – January 2015 ADC34J22 , ADC34J23 , ADC34J24 , ADC34J25

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RGZ|48
- MPQF123F

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RGZ|48
- QFND131R

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9 Detailed Description

9.1 Overview

The ADC34J2x are a high-linearity, ultra-low power, dual-channel, 12-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The ADC34J2x family supports JESD204B interface in order to reduce the number of interface lines, thus allowing for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock, which is used to serialize the 12-bit data from each channel. The ADC34J2x devices support subclass 1 with interface data rates up to 3.2 Gbps.

9.2 Functional Block Diagram

ADC34J22 ADC34J23 ADC34J24 ADC34J25 fbd_sbas669.gif

9.3 Feature Description

9.3.1 Analog Inputs

The ADC34J2x analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-V_PP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 450 MHz (50-Ω source driving 50-Ω termination between INP and INM).

9.3.2 Clock Input

The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 1.4 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADC34J2x can be driven by the transformer-coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in Figure 148, Figure 149, and Figure 150. See Figure 151 for details regarding the internal clock buffer.

ADC34J22 ADC34J23 ADC34J24 ADC34J25 ai_dif_sinewave_clk_bas550.gif

NOTE: R_T = termination resistor, if necessary.

Figure 148. Differential Sine-Wave Clock Driving Circuit

ADC34J22 ADC34J23 ADC34J24 ADC34J25 ai_lvds_clk_drv_bas550.gif

Figure 149. LVDS Clock Driving Circuit

ADC34J22 ADC34J23 ADC34J24 ADC34J25 ai_lvpecl_clk_drv_bas550.gif

Figure 150. LVPECL Clock Driving Circuit

ADC34J22 ADC34J23 ADC34J24 ADC34J25 ai_intclk_buffer_las900.gif

NOTE: C_EQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.

Figure 151. Internal Clock Buffer

A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 152. However, for best performance the clock inputs must be driven differentially, thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input.

ADC34J22 ADC34J23 ADC34J24 ADC34J25 ai_drv_cir_1end_las900.gif

Figure 152. Single-Ended Clock Driving Circuit

9.3.2.1 SNR and Clock Jitter

The signal-to-noise ratio of the ADC is limited by three different factors: quantization noise, thermal noise, and jitter noise, as shown in Equation 1. Quantization noise is typically not noticeable in pipeline converters and is 74 dBFS for a 12-bit ADC.. Thermal noise limits SNR at low input frequencies while the clock jitter sets SNR for higher input frequencies.

Equation 1. ADC34J22 ADC34J23 ADC34J24 ADC34J25 Eq_SNR_CLKJttr_BAS663.gif

The SNR limitation resulting from sample clock jitter can be calculated with Equation 2:

Equation 2. ADC34J22 ADC34J23 ADC34J24 ADC34J25 Eq_SNR_Lmtn_BAS663.gif

The total clock jitter (T_Jitter) has two components: the internal aperture jitter (200 fs for the device) which is set by the noise of the clock input buffer and the external clock. T_Jitter can be calculated with Equation 3:

Equation 3. ADC34J22 ADC34J23 ADC34J24 ADC34J25 Eq_Ttl_Clk_Jttr_BAS663.gif

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input while a faster clock slew rate improves the ADC aperture jitter. The devices have a thermal noise of 73.5 dBFS and internal aperture jitter of 200 fs. The SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 153.

ADC34J22 ADC34J23 ADC34J24 ADC34J25 D036_BAS669.gif

Figure 153. SNR vs Frequency vs Jitter

9.3.2.2 Input Clock Divider

The devices are equipped with an internal divider on the clock input. The divider allows operation with a faster input clock, thus simplifying the system clock distribution design. The clock divider can be bypassed (divide-by-1) for operation with a 160-MHz clock while the divide-by-2 option supports a maximum input clock of 320 MHz and the divide-by-4 option supports a maximum input clock frequency of 640 MHz.

9.3.3 Power-Down Control

The power-down functions of the ADC34J2x can be controlled either through the parallel control pin (PDN) or through an SPI register setting (see Figure 181, register 15h). The PDN pin can also be configured via SPI to a global power-down or standby functionality.

Table 3. Power-Down Modes

FUNCTION	POWER CONSUMPTION (mW)	WAKE-UP TIME (µs)
Global power-down	5	85
Standby	185	35

9.3.4 Internal Dither Algorithm

The ADC34J2x uses an internal dither algorithm to achieve high SFDR and a clean spectrum. However, the dither algorithm marginally degrades SNR, creating a trade-off between SNR and SFDR. If desired, the dither algorithm can be turned off by using the DIS DITH CHx registers bits. Figure 154 and Figure 155 show the effect of using dither algorithms.

ADC34J22 ADC34J23 ADC34J24 ADC34J25 C003_BAS669.png

f_S = 160 MSPS	SNR = 69.7 dBFS
f_IN = 70 MHz	SFDR = 86 dBc

Figure 154. FFT with Dither On

ADC34J22 ADC34J23 ADC34J24 ADC34J25 C004_BAS669.png

f_S = 160 MSPS	SNR = 69.9 dBFS
f_IN = 70 MHz	SFDR = 86 dBc

Figure 155. FFT with Dither Off

9.3.5 JESD204B Interface

The ADC34J2x support device subclass 0, 1, and 2 with a maximum output data rate of 3.2 Gbps for each serial transmitter, as shown in Figure 156. The data of each ADC are serialized by 20x using an internal PLL and then transmitted out on one differential pair each. An external SYSREF (subclass 1) or SYNC (subclass 2) signal is used to align all internal clock phases and the local multiframe clock to a specific sampling clock edge. This process allows synchronization of multiple devices in a system and minimizes timing and alignment uncertainty.

ADC34J22 ADC34J23 ADC34J24 ADC34J25 JESD204B_Intrfc_BAS664.gif

Figure 156. JESD204B Interface

The JESD204B transmitter block consists of the transport layer, the data scrambler, and the link layer, as shown in Figure 157. The transport layer maps the ADC output data into the selected JESD204B frame data format and determines if the ADC output data or test patterns are transmitted. The link layer performs the 8b or 10b data encoding and the synchronization and initial lane alignment using the SYNC input signal. Optionally, data from the transport layer can be scrambled.

ADC34J22 ADC34J23 ADC34J24 ADC34J25 JESD204B_Blck_BAS664.gif

Figure 157. JESD204B Block

9.3.5.1 JESD204B Initial Lane Alignment (ILA)

The initial lane alignment process is started by the receiving device by asserting the SYNC signal. When a logic high is detected on the SYNC input pins, the ADC34J2x starts transmitting comma (K28.5) characters to establish code group synchronization. When synchronization is complete, the receiving device de-asserts the SYNC signal and the ADC34J2x starts the initial lane alignment sequence with the next local multiframe clock boundary. The ADC34J2x transmits four multiframes, each containing K frames (K is SPI programmable). Each multiframe contains the frame start and end symbols; the second multiframe also contains the JESD204 link configuration data.

9.3.5.2 JESD204B Test Patterns

There are three different test patterns available in the transport layer of the JESD204B interface. The ADC34J2x supports a clock output, an encoded, and a PRBS (2¹⁵ – 1) pattern. These patterns can be enabled via SPI register writes and are located in address 2Ah (bits 7:6).

9.3.5.3 JESD204B Frame Assembly

The JESD204B standard defines the following parameters:

L is the number of lanes per link,
M is the number of converters per device,
F is the number of octets per frame clock period, and
S is the number of samples per frame.

Table 4 lists the available JESD204B format and valid range for the ADC34J2x. The ranges are limited by the SERDES line rate and the maximum ADC sample frequency.

Table 4. LMFS Values and Interface Rate

L	M	F	S	MINIMUM ADC SAMPLING RATE (MSPS)	MAXIMUM f_SERDES (Mbps)	MAXIMUM ADC SAMPLING RATE (Msps)	MAXIMUM f_SERDES (GSPS)	MODE
4	4	2	1	15	300	160	3.2	20x (default)
2	4	4	1	10	400	80	3.2	40x

The detailed frame assembly for quad-channel mode is shown in Figure 158. The frame assembly configuration can be changed from 20x (default) to 40x by setting the registers listed in Table 5.

ADC34J22 ADC34J23 ADC34J24 ADC34J25 JESD_Frm_Assmbl_Img2_BAS669.png

Figure 158. JESD Frame Assembly

Table 5. Configuring 40x Mode

ADDRESS	DATA
2Bh	01h
30h	11h

9.3.5.4 Digital Outputs

The ADC34J2x JESD204B transmitter uses differential CML output drivers. The CML output current is programmable from 5 mA to 20 mA using SPI register settings. The output driver expects to drive a differential 100-Ω load impedance and the termination resistors should be placed as close to the receiver inputs as possible to avoid unwanted reflections and signal distortion. Because the JESD204B employs 8b, 10b encoding, the output data stream is dc-balanced and ac-coupling can be used to avoid the need to match up common-mode voltages between the transmitter and receivers. The termination resistors should be connected to the termination voltage as shown in Figure 159.

ADC34J22 ADC34J23 ADC34J24 ADC34J25 Dgtl_Otpts_BAS663.gif

Figure 159. CML Output Connections

Figure 160 shows the data eye measurements of the device JESD204B transmitter against the JESD204B transmitter mask at 3.125 Gbps (156.25 MSPS, 20x mode), respectively.

ADC34J22 ADC34J23 ADC34J24 ADC34J25 eye_3125gbps_las900.gif

Figure 160. Eye Diagram: 3.125 Gbps

9.4 Device Functional Modes

9.4.1 Digital Gain

The input full-scale amplitude can be selected between 1 V_PP to 2 V_PP (default is 2 V_PP) by choosing the appropriate digital gain setting via an SPI register write. Digital gain provides an option to trade-off SNR for SFDR performance. A larger input full-scale increases SNR performance (2 V_PP is recommended for maximum SNR) while reduced input swing typically results in better SFDR performance. Table 6 lists the available digital gain settings.

Table 6. Digital Gain vs Full-Scale Amplitude

DIGITAL GAIN (dB)	MAX INPUT VOLTAGE (V_PP)
0	2.0
0.5	1.89
1	1.78
1.5	1.68
2	1.59
2.5	1.50
3	1.42
3.5	1.34
4	1.26
4.5	1.19
5	1.12
5.5	1.06
6	1.00

9.4.2 Overrange Indication

The ADC34J2x provides two different overrange indications. The normal OVR (default) is triggered if the final 14- bit data output exceeds the maximum code value. The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and is presented after just nine clock cycles, thus enabling a quicker reaction to an overrange event. By default, the normal overrange indication is output on the OVRx pins (where x is A, B, C, or D). The fast OVR indication can be presented on the overrange pins instead by using the SPI register map.

9.5 Programming

The ADS34Jxx can be configured using a serial programming interface, as described in this section.

9.5.1 Serial Interface

The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.

9.5.1.1 Register Initialization

After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin (of durations greater than 10 ns), as shown in Figure 161. If required, the serial interface registers can be cleared during operation either:

Through a hardware reset, or
By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low.

9.5.1.1.1 Serial Register Write

The device internal register can be programmed with these steps:

Drive the SEN pin low,
Set the R/W bit to 0 (bit A15 of the 16-bit address),
Set bit A14 in the address field to 1,
Initiate a serial interface cycle by specifying the address of the register (A13 to A0) whose content must be written, and
Write the 8-bit data that are latched in on the SCLK rising edge.

Figure 161 and Table 7 show the timing requirements for the serial register write operation.

ADC34J22 ADC34J23 ADC34J24 ADC34J25 Srl_Rgstr_wrt_Tmg_BAS663.gif

Figure 161. Serial Register Write Timing Diagram

Table 7. Serial Interface Timing⁽¹⁾

PARAMETER		MIN	MAX	UNIT
f_SCLK	SCLK frequency (equal to 1 / t_SCLK)	> dc	20	MHz
t_SLOADS	SEN to SCLK setup time	25		ns
t_SLOADH	SCLK to SEN hold time	25		ns
t_DSU	SDIO setup time	25		ns
t_DH	SDIO hold time	25		ns

(1) Typical values are at 25°C, full temperature range is from T_MIN = –40°C to T_MAX = 85°C, and AVDD = DVDD = 1.8 V, unless otherwise noted.

9.5.1.1.2 Serial Register Readout

The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin. This readback mode may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. Given below is the procedure to read contents of serial registers:

Drive the SEN pin low.
Set the R/W bit (A15) to 1. This setting disables any further writes to the registers.
Set bit A14 in the address field to 1.
Initiate a serial interface cycle specifying the address of the register (A13 to A0) whose content must be read.
The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin.
The external controller can latch the contents at the SCLK rising edge.
To enable register writes, reset the R/W register bit to 0.

When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the SDOUT pin must float. Figure 162 shows a timing diagram of the serial register read operation. Data appear on the SDOUT pin at the SCLK falling edge with an approximate delay (t_{SD_DELAY}) of 20 ns, as shown in Figure 163.

ADC34J22 ADC34J23 ADC34J24 ADC34J25 Srl_Rgstr_Rd_Tmg_BAS663.gif

Figure 162. Serial Register Read Timing Diagram

ADC34J22 ADC34J23 ADC34J24 ADC34J25 ai_tim_sdout_las900.gif

Figure 163. SDOUT Timing Diagram

9.5.2 Register Initialization

After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin, as shown in Figure 164 and Table 8.

ADC34J22 ADC34J23 ADC34J24 ADC34J25 Rgstr_Intlztn_BAS663.gif

Figure 164. Initialization of Serial Registers after Power-Up

Table 8. Power-Up Timing

PARAMETER		CONDITIONS	MIN	MAX	UNIT
t₁	Power-on delay	Delay from power up to active high RESET pulse	1		ms
t₂	Reset pulse width	Active high RESET pulse width	10	1000	ns
t₃	Register write delay	Delay from RESET disable to SEN active	100		ns

If required, the serial interface registers can be cleared during operation either:

Through hardware reset, or
By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low.

9.5.3 Start-Up Sequence

After power-up, the sequence described in Table 9 can be used to set up the ADC34J2x for basic operation.

Table 9. Start-Up Settings

STEP	DESCRIPTION	REGISTER ADDRESS AND DATA
1	Bring up all supply voltages. There is no required power supply sequence for AVDD and DVDD	—
2	Pulse hardware reset (low to high to low) on pin 24	—
3	Optional configure LMFS of JESD204B interface to LMFS = 2441 (default is LMFS = 4421)	Address 2Bh, data 01h Address 30h, data 11h
4	Pulse SYNC~ from high to low to transmit data from k28.5 sync mode	—

9.6 Register Map

Table 10. Serial Register Map

REGISTER ADDRESS	REGISTER DATA
A[13:0] (Hex)	7	6	5	4	3	2	1	0
01	DIS DITH CHA		DIS DITH CHB		DIS DITH CHC		DIS DITH CHD
02	0	0	0	0	0	0	CHA GAIN EN	0
03	0	0	0	0	0	0	CHB GAIN EN	0
04	0	0	0	0	0	0	CHC GAIN EN	0
05	0	0	0	0	0	0	CHD GAIN EN	0
06	0	0	0	SPECIAL MODE1 CHA			TEST PATTERN EN	RESET
07	0	0	0	SPECIAL MODE1 CHB			EN FOVR	0
08	0	0	0	SPECIAL MODE1 CHC			0	0
09	0	0	0	SPECIAL MODE1 CHD			ALIGN TEST PATTERN	DATA FORMAT
0A	CHA TEST PATTERN				CHB TEST PATTERN
0B	CHC TEST PATTERN				CHD TEST PATTERN
0C	CHA DIGITAL GAIN				CHB DIGITAL GAIN
0D	CHC DIGITAL GAIN				CHD DIGITAL GAIN
0E	CUSTOM PATTERN[11:4]
0F	CUSTOM PATTERN [3:0]				0	0	0	0
13	LOW SPEED MODE	0	0	0	0	0	0	0
15	CHA PDN	CHB PDN	CHC PDN	CHD PDN	STANDBY	GLOBAL PDN	0	PDN PIN DISABLE
27	CLK DIV		0	0	0	0	0	0
2A	SERDES TEST PATTERN		IDLE SYNC	TRP LAYER TESTMODE EN	FLIP ADC DATA	LANE ALIGN	FRAME ALIGN	TXMIT LINKDATA DIS
2B	0	0	0	0	0	0	CTRL K	CTRL F
2F	SCR (SCR EN)	0	0	0	0	0	0	0
30	OCTETS PER FRAME
31	0	0	0	FRAMES PER MULTI FRAME
34	SUBCLASSV			0	0	0	0	0
3A	SYNC REQ	OPTION SYNC REG	0	0	OUTPUT CURRENT SEL
3B	LINK LAYER TESTMODE SEL[2:0]			LINK LAYER RPAT	0	PULSE DET MODES
3C	FORCE LMFC COUNT	LMFC COUNT INIT					LMFC COUNT INIT
122	0	0	0	0	0	0	SPECIAL MODE2 CHA [1:0]
134	0	0	DIS DITH CHA	0	DIS DITH CHA	0	0	0
222	0	0	0	0	0	0	SPECIAL MODE2 CHD [1:0]
234	0	0	DIS DITH CHD	0	DIS DITH CHD	0	0	0
422	0	0	0	0	0	0	SPECIAL MODE2 CHB [1:0]
434	0	0	DIS DITH CHB	0	DIS DITH CHB	0	0	0
522	0	0	0	0	0	0	SPECIAL MODE2 CHC [1:0]
534	0	0	DIS DITH CHC	0	DIS DITH CHC	0	0	0

9.6.1 Serial Register Description

Figure 165. Register 01h

7	6	5	4	3	2	1	0
DIS DITH CHA		DIS DITH CHB		DIS DITH CHC		DIS DITH CHD

Table 11. Register 01h Description

Name	Description
Bits 7:6	DIS DITH CHA
	00 = Default 11 = Dither is disabled, high SNR mode is selected for channel A. In this mode, SNR typically improves by 0.3 dB at 70 MHz. Ensure that register 134 (bits 5 and 3) are also set to 11.
Bits 5:4	DIS DITH CHB
	00 = Default 11 = Dither is disabled, high SNR mode is selected for channel B. In this mode, SNR typically improves by 0.3 dB at 70 MHz. Ensure that register 434 (bits 5 and 3) are also set to 11.
Bits 3:2	DIS DITH CHC
	00 = Default 11 = Dither is disabled, high SNR mode is selected for channel C. In this mode, SNR typically improves by 0.3 dB at 70 MHz. Ensure that register 534 (bits 5 and 3) are also set to 11.
Bits 1:0	DIS DITH CHD
	00 = Default 11 = Dither is disabled, high SNR mode is selected for channel D. In this mode, SNR typically improves by 0.3 dB at 70 MHz. Ensure that register 234 (bits 5 and 3) are also set to 11.

Figure 166. Register 02h

7	6	5	4	3	2	1	0
0	0	0	0	0	0	CHA GAIN EN	0

Table 12. Register 02h Description

Name	Description
Bits 7:2	Must write 0
Bit 1	CHA GAIN EN
	Enable digital gain control for channel A. 0 = Default 1 = Digital gain for channel A can be programmed with the CHA DIGITAL GAIN bits.
Bit 0	Must write 0

Figure 167. Register 03h

7	6	5	4	3	2	1	0
0	0	0	0	0	0	CHB GAIN EN	0

Table 13. Register 03h Description

Name	Description
Bits 7:2	Must be 0
Bit 1	CHB GAIN EN:
	Enable digital gain control for channel B. 0 = Default 1 = Digital gain for channel B can be programmed with the CHB DIGITAL GAIN bits.
Bit 0	Must write 0

Figure 168. Register 04h

7	6	5	4	3	2	1	0
0	0	0	0	0	0	CHC GAIN EN	0

Table 14. Register 04h Description

Name	Description
Bits 7:2	Must write 0
Bit 1	CHC GAIN EN
	Enable digital gain control for channel C. 0 = Default 1 = Digital gain for channel C can be programmed with the CHC DIGITAL GAIN bits.
Bit 0	Must write 0

Figure 169. Register 05h

7	6	5	4	3	2	1	0
0	0	0	0	0	0	CHD GAIN EN	0

Table 15. Register 05h Description

Name	Description
Bits 7:2	Must write 0
Bit 1	CHD GAIN EN:
	Enable digital gain control for channel D 0 = Default 1 = Digital gain for channel D can be programmed with the CHD DIGITAL GAIN bits.
Bit 0	Must write 0

Figure 170. Register 06h

7	6	5	4	3	2	1	0
0	0	0	SPECIAL MODE1 CHA			TEST PATTERN EN	RESET

Table 16. Register 06h Description

Name	Description
Bits 7:5	Must write 0
Bits 4:2	SPECIAL MODE1 CHA
	010 = For frequencies < 120 MHz 111 = For frequencies > 120 MHz
Bit 1	TEST PATTERN EN
	This bit enables test pattern selection for the digital outputs. 0 = Normal operation 1 = Test pattern output enabled
Bit 0	RESET: Software reset applied
	This bit resets all internal registers to the default values and self-clears to 0.

Figure 171. Register 07h

7	6	5	4	3	2	1	0
0	0	0	SPECIAL MODE1 CHB			EN FOVR	0

Table 17. Register 07h Description

Name	Description
Bits 7:5	Must write 0
Bits 4:2	SPECIAL MODE1 CHB
	010 = For frequencies < 120 MHz 111 = For frequencies > 120 MHz
Bit 1	EN FOVR
	0 = Normal OVR on OVRx pins 1 = Enable fast OVR on OVRx pins
Bit 0	Must write 0

Figure 172. Register 08h

7	6	5	4	3	2	1	0
0	0	0	SPECIAL MODE1 CHC			0	0

Table 18. Register 08h Description

Name	Description
Bits 7:5	Must write 0
Bits 4:2	SPECIAL MODE1 CHC
	010 = For frequencies < 120 MHz 111 = For frequencies > 120 MHz
Bits 1:0	Must write 0

Figure 173. Register 09h

7	6	5	4	3	2	1	0
0	0	0	SPECIAL MODE1 CHD			ALIGN TEST PATTERN	DATA FORMAT

Table 19. Register 09h Description

Name	Description
Bits 7:5	Must write 0
Bits 4:2	SPECIAL MODE1 CHD
	010 = For frequencies < 120 MHz 111 = For frequencies > 120 MHz
Bit 1	ALIGN TEST PATTERN
	This bit aligns test patterns across the outputs of four channels. 0 = Test patterns of four channels are free running. 1 = Test patterns of four channels are aligned.
Bit 0	DATA FORMAT: Digital output data format
	0 = Twos complement 1 = Offset binary

Figure 174. Register 0Ah

7	6	5	4	3	2	1	0
CHA TEST PATTERN				CHB TEST PATTERN

Table 20. Register 0Ah Description

Name	Description
Bits 7:4	CHA TEST PATTERN
	These bits control the test pattern for channel A after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101. 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 4095. 0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits. 0110 = Deskew pattern: data are AAAh. 1000 = PRBS pattern: data are a sequence of pseudo random numbers. 1001 = 8-point sine wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 599, 2048, 3496, 4095, 3496, 2048, 599. Others = Do not use
Bits 3:0	CHB TEST PATTERN
	These bits control the test pattern for channel B after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101. 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 4095. 0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits. 0110 = Deskew pattern: data are AAAh. 1000 = PRBS pattern: data are a sequence of pseudo random numbers. 1001 = 8-point sine wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 599, 2048, 3496, 4095, 3496, 2048, 599. Others = Do not use

Figure 175. Register 0Bh

7	6	5	4	3	2	1	0
CHC TEST PATTERN				CHD TEST PATTERN

Table 21. Register 0Bh Description

Name	Description
Bits 7:4	CHC TEST PATTERN
	These bits control the test pattern for channel C after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101. 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 4095. 0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits. 0110 = Deskew pattern: data are AAAh. 1000 = PRBS pattern: data are a sequence of pseudo random numbers. 1001 = 8-point sine wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 599, 2048, 3496, 4095, 3496, 2048, 599. Others = Do not use
Bits 3:0	CHD TEST PATTERN
	These bits control the test pattern for channel D after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101. 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 4095. 0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits. 0110 = Deskew pattern: data are AAAh. 1000 = PRBS pattern: data are a sequence of pseudo random numbers. 1001 = 8-point sine wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 599, 2048, 3496, 4095, 3496, 2048, 599. Others = Do not use

Figure 176. Register 0Ch

7	6	5	4	3	2	1	0
CHA TEST PATTERN				CHB TEST PATTERN

Table 22. Register 0Ch Description

Name	Description
Bits 7:4	CHA TEST PATTERN
	In address 0Ch, these bits control the test pattern for channel A after the CHA GAIN EN bit is set. See Table 23 for register settings.
Bits 3:0	CHB TEST PATTERN
	In address 0Ch, these bits control the test pattern for channel B after the CHB GAIN EN bit is set. See Table 23 for register settings.

Table 23. Channel Digital Gain

REGISTER VALUE	DIGITAL GAIN (dB)	MAXIMUM INPUT VOLTAGE (V_PP)
0000	0	2.0
0001	0.5	1.89
0010	1	1.78
0011	1.5	1.68
0100	2	1.59
0101	2.5	1.50
0110	3	1.42
0111	3.5	1.34
1000	4	1.26
1001	4.5	1.19
1010	5	1.12
1011	5.5	1.06
1100	6	1.00

Figure 177. Register 0Dh

7	6	5	4	3	2	1	0
CHC TEST PATTERN				CHD TEST PATTERN

Table 24. Register 0Dh Description

Name	Description
Bits 7:4	CHC TEST PATTERN
	In address 0Dh, these bits control the test pattern for channel C after the CHC GAIN EN bit is set. See Table 23 for register settings.
Bits 3:0	CHD TEST PATTERN
	In address 0Dh, these bits control the test pattern for channel D after the CHD GAIN EN bit is set. See Table 23 for register settings.

Figure 178. Register 0Eh

7	6	5	4	3	2	1	0
CUSTOM PATTERN[11:4]

Table 25. Register 0Eh Description

Name	Description
Bits 7:0	CUSTOM PATTERN[11:4]
	These bits set the 14-bit custom pattern (11:4) for all channels.

Figure 179. Register 0Fh

7	6	5	4	3	2	1	0
CUSTOM PATTERN[3:0]				0	0	0	0

Table 26. Register 0Fh Description

Name	Description
Bits 7:2	CUSTOM PATTERN[3:0]
	These bits set the 14-bit custom pattern (3:0) for all channels.
Bits 3:0	Must write 0

Figure 180. Register 13h

7	6	5	4	3	2	1	0
LOW SPEED MODE	0	0	0	0	0	0	0

Table 27. Register 13h Description

Name	Description
Bit 7	LOW SPEED MODE
	Use this bit for sampling frequencies < 25 MSPS. 0 = Normal operation 1 = Low-speed mode enabled
Bits 6:0	Must write 0

Figure 181. Register 15h

7	6	5	4	3	2	1	0
CHA PDN	CHB PDN	CHC PDN	CHD PDN	STANDBY	GLOBAL PDN	0	CONFIG PDN PIN

Table 28. Register 15h Description

Name	Description
Bit 7	CHA PDN: Power-down channel A
	0 = Normal operation 1 = Power-down channel A
Bit 6	CHB PDN: Power-down channel B
	0 = Normal operation 1 = Power-down channel B
Bit 5	CHC PDN: Power-down channel C
	0 = Normal operation 1 = Power-down channel C
Bit 4	CHD PDN: Power-down channel D
	0 = Normal operation 1 = Power-down channel D
Bit 3	STANDBY
	This bit places the ADCs of all four channels into standby. 0 = Normal operation 1 = Standby
Bit 2	GLOBAL PDN
	Places device in global power down. 0 = Normal operation 1 = Global power-down
Bit 1	Must write 0
Bit 0	CONFIG PDN PIN
	This bit configures the PDN pin as either global power-down or standby pin. 0 = Logic high voltage on the PDN pin sends places the into global power-down. 1 = Logic high voltage on the PDN pin places the device into standby.

Figure 182. Register 27h

7	6	5	4	3	2	1	0
CLK DIV		0	0	0	0	0	0

Table 29. Register 27h Description

Name	Description
Bits 7:6	CLK DIV: Internal clock divider for the input sampling clock
	00 = Clock divider bypassed 01 = Divide-by-1 10 = Divide-by-2 11 = Divide-by-4
Bits 5:0	Must write 0

Figure 183. Register 2Ah

7	6	5	4	3	2	1	0
SERDES TEST PATTERN		IDLE SYNC	TESTMODE EN	FLIP ADC DATA	LANE ALIGN	FRAME ALIGN	TX LINK CONFIG DATA DIS

Table 30. Register 2Ah Description

Name	Description
Bits 7:6	SERDES TEST PATTERN:
	These bits set the test patterns in the transport layer of the JESD204B interface. 00 = Normal operation 01 = Outputs clock pattern (output is 10101010) 10 = Encoded pattern (output is 1111111100000000) 11 = Output is 2¹⁵ – 1
Bit 5	IDLE SYNC
	This bit generates the long transport layer test pattern mode according to 5.1.6.3 clause of JESD204B specification. 0 = Test mode disabled 1 = Test mode enabled
Bit 4	TESTMODE EN
	This bit sets the output pattern when SYNC is high. 0 = Sync code is k28.5 (0xBCBC) 1 = Sync code is 0xBC50
Bit 3	FLIP ADC DATA
	This bit sets the output pattern when SYNC is high. 0 = Normal operation 1 = Output data order is reversed: MSB – LSB
Bit 2	LANE ALIGN
	This bit inserts a lane alignment character (K28.3) for the receiver to align to the lane boundary per section 5.3.3.5 of the JESD204B specification. 0 = Normal operation 1 = Inserts lane alignment characters
Bit 1	FRAME ALIGN
	This bit inserts a frame alignment character (K28.7) for the receiver to align to the frame boundary per section 5.3.3.4 of the JESD204B specification. 0 = Normal operation 1 = Inserts frame alignment characters
Bit 0	TX LINK CONFIG DATA DIS
	This bit disables the initial link alignment (ILA) sequence when SYNC is de-asserted. 0 = Normal operation 1 = ILA disabled

Figure 184. Register 2Bh

7	6	5	4	3	2	1	0
0	0	0	0	0	0	CTRL K	CTRL F

Table 31. Register 2Bh Description

Name	Description
Bits 7:2	Must write 0
Bit 1	CTRL K: Enable bit for number of frames per multiframe
	0 = Default is 9 frames (20x mode) per multiframe 1 = Frames per multiframe can be set in register 31h
Bit 0	CTRL F: Enable bit for number of octets per frame
	0 = 20x mode using one lane per ADC (default is F = 2) 1 = Octets per frame can be specified in register 30h

Figure 185. Register 2Fh

7	6	5	4	3	2	1	0
SCRAMBLE EN	0	0	0	0	0	0	0

Table 32. Register 2Fh Description

Name	Description
Bit 7	SCRAMBLE EN
	This bit scrambles the enable bit in the JESD204B interface. 0 = Scrambling disabled 1 = Scrambling enabled
Bits 6:0	Must write 0

Figure 186. Register 30h

7	6	5	4	3	2	1	0
OCTETS PER FRAME

Table 33. Register 30h Description

Name	Description
Bits 7:0	OCTETS PER FRAME
	These bits set the number of octets per frame (F). 01 = 20x serialization: two octets per frame 11 = 40x serialization: four octets per frame

Figure 187. Register 31h

7	6	5	4	3	2	1	0
0	0	0	FRAMES PER MULTI FRAME

Table 34. Register 31h Description

Name	Description
Bits 7:5	Must write 0
Bits 4:0	FRAMES PER MULT IFRAME
	These bits set the number of frames per multiframe. After reset, the default settings for frames per multiframe are: 20x mode: K = 8 (for each mode, K should not be set to a lower value).

Figure 188. Register 34h

7	6	5	4	3	2	1	0
SUBCLASS			0	0	0	0	0

Table 35. Register 34h Description

Name	Description
Bits 7:5	SUBCLASS
	These bits set the JESD204B subclass. 000 = Subclass 0 (backward compatibility with JESD204A) 001 = Subclass 1 (deterministic latency using SYSREF signal) 010 = Subclass 2 (deterministic latency using SYNC detection)
Bits 4:0	Must write 0

Figure 189. Register 3Ah

7	6	5	4	3	2	1	0
SYNC REQ	SYNC REQ EN	0	0	OUTPUT CURRENT SEL

Table 36. Register 3Ah Description

Name	Description
Bit 7	SYNC REQ
	This bit generates a synchronization request only when the SYNC REQ EN register bit is set. 0 = Normal operation 1 = Generates sync request
Bit 6	SYNC REQ EN
	0 = Sync request is made with the SYNCP~, SYNCM~ pins 1 = Sync request is made with the SYNC REQ register bit
Bits 5:4	Must write 0
Bits 3:0	OUTPUT CURRENT SEL: JESD output buffer current selection
	Program current (mA) 000 =16 001 = 12 010 = 8 011 = 4	100 = 32 101 = 28 110 = 24 111 = 20

Figure 190. Register 3Bh

7	6	5	4	3	2	1	0
LINK LAYER TESTMODE			LINK LAYER RPAT	0	PULSE DET MODES

Table 37. Register 3Bh Description

Name	Description
Bits 7:5	LINK LAYER TESTMODE
	These bits generate a pattern according to clause 5.3.3.8.2 of the JESD204B document. 000 = Normal ADC data 001 = D21.5 (high frequency jitter pattern) 010 = K28.5 (mixed frequency jitter pattern) 011 = Repeat initial lane alignment (generates K28.5 character and repeat lane alignment sequences continuously) 100 = 12 octet RPAT jitter pattern
Bit 4	LINK LAYER RPAT
	This bit changes the running disparity in the modified RPAT pattern test mode (only when link layer test mode = 100). 0 = normal operation 1 = changes disparity
Bit 3	Must write 0
Bits 2:0	PULSE DET MODES
	These bits select different detection modes for SYSREF (subclass 1) and SYNC (subclass2).

Table 38. PULSE DET MODES Register Settings

D2	D1	D0	FUNCTIONALITY
0	Don’t care	0	Allow all pulses to reset input clock dividers
1	Don’t care	0	Do not allow reset of analog clock dividers
Don’t care	0 to 1 transition	1	Allow one pulse immediately after the 0 to1 transition to reset the divider

Figure 191. Register 3Ch

7	6	5	4	3	2	1	0
FORCE LMFC COUNT	LMFC COUNT INIT					RELEASE ILANE SEQ

Table 39. Register 3Ch Description

Name	Description
Bit 7	FORCE LMFC COUNT: Force LMFC count
	0 = Normal operation 1 = Enables using different starting values for the LMFC counter
Bits 6:2	LMFC COUNT INIT
	If SYSREF is transmitted to the digital block, the LMFC count resets to 0 and K28.5 stops transmitting when the LMFC count reaches 31. The initial value that the LMFC count resets to can be set using LMFC COUNT INIT. In this manner, the Rx can be synchronized early because the Rx receives the LANE ALIGNMENT SEQUENCE early. The FORCE LMFC COUNT register bit must be enabled.
Bits 1:0	RELEASE ILANE SEQ
	These bits delay the lane alignment sequence generation by 0, 1, 2, or 3 multiframes after the code group synchronization. 00 = 0 01 = 1 10 = 2 11 = 3

Figure 192. Register 122h

7	6	5	4	3	2	1	0
0	0	0	0	0	0	SPECIAL MODE2 CHA [1:0]

Table 40. Register 122h Description

Name	Description
Bits 7:2	Must write 0
Bit 1:0	SPECIAL MODE2 CHA [1:0]
	Always write '11' for better HD2 performance.

Figure 193. Register 134h

7	6	5	4	3	2	1	0
0	0	DIS DITH CHA	0	DIS DITH CHA	0	0	0

Table 41. Register 134h Description

Name	Description
Bits 7:6	Must write 0
Bit 5	DIS DITH CHA
	00 = Default 11 = Dither is disabled and high SNR mode is selected for channel A. In this mode, SNR typically improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 7:6) are also set to 11.
Bit 4	Must write 0
Bit 3	DIS DITH CHA
	00 = Default 11 = Dither is disabled and high SNR mode is selected for channel A. In this mode, SNR typically improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 7:6) are also set to 11.
Bits 2:0	Must write 0

Figure 194. Register 222h

7	6	5	4	3	2	1	0
0	0	0	0	0	0	SPECIAL MODE 2 CHD [1:0]

Table 42. Register 222h Description

Name	Description
Bits 7:2	Must write 0
Bit 1:0	SPECIAL MODE 2 CHD [1:0]
	Always write '11' for better HD2 performance.

Figure 195. Register 234h

7	6	5	4	3	2	1	0
0	0	DIS DITH CHD	0	DIS DITH CHD	0	0	0

Table 43. Register 234h Description

Name	Description
Bits 7:6	Must write 0
Bit 5	DIS DITH CHD
	00 = Default 11 = Dither is disabled and high SNR mode is selected for channel D. In this mode, SNR typically improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 1:0) are also set to 11.
Bit 4	Must write 0
Bit 3	DIS DITH CHD
	00 = Default 11 = Dither is disabled and high SNR mode is selected for channel D. In this mode, SNR typically improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 1:0) are also set to 11.
Bits 2:0	Must write 0

Figure 196. Register 422h

7	6	5	4	3	2	1	0
0	0	0	0	0	0	SPECIAL MODE 2 CHB [1:0]

Table 44. Register 422h Description

Name	Description
Bits 7:2	Must write 0
Bit 1:0	SPECIAL MODE 2 CHB [1:0]
	Always write '11' for better HD2 performance.

Figure 197. Register 434h

7	6	5	4	3	2	1	0
0	0	DIS DITH CHB	0	DIS DITH CHB	0	0	0

Table 45. Register 434h Description

Name	Description
Bits 7:6	Must write 0
Bit 5	DIS DITH CHB
	00 = Default 11 = Dither is disabled and high SNR mode is selected for channel B. In this mode, SNR typically improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 5:4) are also set to 11.
Bit 4	Must write 0
Bit 3	DIS DITH CHB
	00 = Default 11 = Dither is disabled and high SNR mode is selected for channel B. In this mode, SNR typically improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 5:4) are also set to 11.
Bits 2:0	Must write 0

Figure 198. Register 522h

7	6	5	4	3	2	1	0
0	0	0	0	0	0	SPECIAL MODE 2 CHC [1:0]

Table 46. Register 522h Description

Name	Description
Bits 7:2	Must write 0
Bit 1:0	SPECIAL MODE 2 CHC [1:0]
	Always write '11' for better HD2 performance.

Figure 199. Register 534h

7	6	5	4	3	2	1	0
0	0	DIS DITH CHC	0	DIS DITH CHC	0	0	0

Table 47. Register 534h Description

Name	Description
Bits 7:6	Must write 0
Bit 5	DIS DITH CHC
	00 = Default 11 = Dither is disabled and high SNR mode is selected for channel C. In this mode, SNR typically improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 3:2) are also set to 11.
Bit 4	Must write 0
Bit 3	DIS DITH CHC
	00 = Default 11 = Dither is disabled and high SNR mode is selected for channel C. In this mode, SNR typically improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 3:2) are also set to 11.
Bits 2:0	Must write 0