ZHCSLJ1C July   2020  – December 2022 ADC3541 , ADC3542 , ADC3543

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications ADC3541
    8. 6.8  Electrical Characteristics - AC Specifications ADC3542
    9. 6.9  Electrical Characteristics - AC Specifications ADC3543
    10. 6.10 Timing Requirements
    11. 6.11 Typical Characteristics: ADC3541
    12. 6.12 Typical Characteristics: ADC3542
    13. 6.13 Typical Characteristics: ADC3543
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Single Ended Input
          3. 8.3.1.2.3 Analog Input Termination and DC Bias
            1. 8.3.1.2.3.1 AC-Coupling
            2. 8.3.1.2.3.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 Digital Filter Operation
        2. 8.3.4.2 FS/4 Mixing with Real Output
        3. 8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
        4. 8.3.4.4 Decimation Filter
        5. 8.3.4.5 SYNC
        6. 8.3.4.6 Output Formatting with Decimation
          1. 8.3.4.6.1 Parallel CMOS
          2. 8.3.4.6.2 Serialized CMOS Interface
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Parallel CMOS Output
        2. 8.3.5.2 Serialized CMOS output
          1. 8.3.5.2.1 SDR Output Clocking
        3. 8.3.5.3 Output Data Format
        4. 8.3.5.4 Output Formatter
        5. 8.3.5.5 Output Bit Mapper
        6. 8.3.5.6 Output Interface/Mode Configuration
          1. 8.3.5.6.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration Using the SPI Interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Map
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Signal Path
        2. 9.2.2.2 Sampling Clock
        3. 9.2.2.3 Voltage Reference
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Set Up
      1. 9.3.1 Register Initialization During Operation
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.6.1 Detailed Register Description

Figure 8-52 Register 0x00
76543210
0000000RESET
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-16 Register 0x00 Field Descriptions
BitFieldTypeResetDescription
7-10R/W0Must write 0
0RESETR/W0This bit resets all internal registers to the default values and self clears to 0.
Figure 8-53 Register 0x07
76543210
OP IF MAPPER0OP IF ENOP IF SEL
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-17 Register 0x07 Field Descriptions
BitFieldTypeResetDescription
7-5OP IF MAPPERR/W000This register contains the proper output interface bit mapping for the different interfaces. The interface bit mapping is internally loaded from e-fuses and also requires a fuse load command to go into effect (0x13, D0). Register 0x07 along with the E-Fuse Load (0x13, D0) needs to be loaded first in the programming sequence since the E-Fuse load resets the SPI writes.
After initial reset the default output interface variant is loaded automatically from fuse internally. However when reading back this register reads 000 until a value is written using SPI.
001: 2-wire, 18 and 14-bit
010: 2-wire, 16-bit
011: 1-wire
100: 0.5-wire
101: DDR
110: SDR
40R/W0Must write 0
3OP IF ENR/W0Enables changing the default output interface mode (D2-D0).
2-0OP IF SELR/W000Selects the output interface mode. OP IF EN (D3) needs to be enabled also.After initial reset the default output interface is loaded automatically from fuse internally. However when reading back this register reads 000 until a value is written using SPI.
000: SDR CMOS
001: DDR CMOS
011: 2-wire
100: 1-wire
101: 0.5-wire
others: not used
Figure 8-54 Register 0x08
76543210
00PDN CLKBUFPDN REFAMP0PDN A1PDN GLOBAL
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-18 Register 0x08 Field Descriptions
BitFieldTypeResetDescription
7-60R/W0Must write 0
5PDN CLKBUFR/W0Powers down sampling clock buffer
0: Clock buffer enabled
1: Clock buffer powered down
4PDN REFAMPR/W0Powers down internal reference gain amplifier
0: REFAMP enabled
1: REFAMP powered down
30R/W0Must write 0
2PDN AR/W0Powers down ADC channel A
0: ADC channel A enabled
1: ADC channel A powered down
11R/W1Must write 1
0PDN GLOBALR/W0Global power down via SPI
0: Global power disabled
1: Global power down enabled. Power down mask (register 0x0D) determines which internal blocks are powered down.
Figure 8-55 Register 0x0A, B, C
76543210
CMOS OB DIS [23:0]
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-19 Register 0x0A/B/C Field Descriptions
BitFieldTypeResetDescription
7:0CMOS OB DIS [23:0]R/W0These register bits power down the individual CMOS output buffers. See Table 8-20 for the actual bit to pin mapping. Unused pins should be powered down (ie set to 1) for maximum power savings.
There is a separate control to enable the DCLKIN buffer in register 0x1F (D6) and 0x18 (D4). DCLK output buffer is powered down using register 0x1F (D4).
NOTE: When using serial CMOS interface the CMOS output buffer (D3) has to be powered down because it shares the pin with DCLKIN.
0: Output buffer enabled
1: Output buffer powered down
Table 8-20 Output buffer enable bit mapping vs output interface mode
ADDRESS (HEX)BITPIN NAMESDR CMOSDDR CMOSSCMOS 2-wSCMOS 1-w
0x0AD7D7D7D7--
D6-----
D5-----
D4D4D4---
D3D3D3-DCLKINDCLKIN
D2D2D2---
D1D1D1---
D0D0D0---
Register setting0x600x7F0xFF0xFF
0x0BD7D13D13---
D6D14D14---
D5D15D15---
D4FCLK--FCLKFCLK
D3-----
D2-----
D1-----
D0D8D8D8--
Register setting0x1E0xFE0xEF0xEF
0x0CD7D10D10D10--
D6D9D9D9--
D5D6D6D6--
D4D5D5D5--
D3-----
D2-----
D1D11D11D11D11D11
D0D12D12D12D12-
Register setting0x0C0x0C0xFC0xFD
Figure 8-56 Register 0x0D (PDN GLOBAL MASK)
76543210
00MASK REFSYS A0MASK CLKBUFMASK REFAMPMASK BG DIS0
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-21 Register 0x0D Field Descriptions
BitFieldTypeResetDescription
70R/W0Must write 0
60R/W0Must write 0
5MASK REFSYS AR/W0Global power down mask control for internal bias currents, ADC channel A.
0: Internal bias currents will get powered down when global power down is exercised.
1: Internal bias currents will NOT get powered down when global power down is exercised.
40R/W0Must write 0
3MASK CLKBUFR/W0Global power down mask control for sampling clock input buffer.
0: Clock buffer will get powered down when global power down is exercised.
1: Clock buffer will NOT get powered down when global power down is exercised.
2MASK REFAMPR/W0Global power down mask control for reference amplifier.
0: Reference amplifier will get powered down when global power down is exercised.
1: Reference amplifier will NOT get powered down when global power down is exercised.
1MASK BG DISR/W0Global power down mask control for internal 1.2V bandgap voltage reference. Setting this bit reduces power consumption in global power down mode but increases the wake up time. See the power down option overview.
0: Internal 1.2V bandgap voltage reference will NOT get powered down when global power down is exercised.
1: Internal 1.2V bandgap voltage reference will get powered down when global power down is exercised.
00R/W0Must write 0
Figure 8-57 Register 0x0E
76543210
SYNC PIN ENSPI SYNCSPI SYNC EN0REF CTLREF SELSE CLK EN
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-22 Register 0x0E Field Descriptions
BitFieldTypeResetDescription
7SYNC PIN ENR/W0This bit controls the functionality of the SYNC/PDN pin.
0: SYNC/PDN pin exercises global power down mode when pin is pulled high.
1: SYNC/PDN pin issues the SYNC command when pin is pulled high.
6SPI SYNCR/W0Toggling this bit issues the SYNC command using the SPI register write. SYNC using SPI must be enabled as well (D5). This bit doesn't self reset to 0.
0: Normal operation
1: SYNC command issued.
5SPI SYNC ENR/W0This bit enables synchronization using SPI instead of the SYNC/PDN pin.
0: Synchronization using SPI register bit disabled.
1: Synchronization using SPI register bit enabled.
40R/W0Must write 0
3REF CTLR/W0This bit determines if the REFBUF pin controls the voltage reference selection or the SPI register (D2-D1).
0: The REFBUF pin selects the voltage reference option.
1: Voltage reference is selected using SPI (D2-D1) and single ended clock using D0.
2-1REF SELR/W00Selects of the voltage reference option. REF CTRL (D3) must be set to 1.
00: Internal reference
01: External voltage reference (1.2V) using internal reference buffer (REFBUF)
10: External voltage reference
11: not used
0SE CLK ENR/W0Selects single ended clock input and powers down the differential sampling clock input buffer. REF CRTL (D3) must be set to 1.
0: Differential clock input
1: Single ended clock input
Figure 8-58 Register 0x11
76543210
00SE A00DLL PDN0AZ EN
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-23 Register 0x11 Field Descriptions
BitFieldTypeResetDescription
7-60R/W0Must write 0
5SE AR/W0This bit enables single ended analog input, channel A. In this mode the SNR reduces by 3-dB.
0: Differential input
1: Single ended input.
4-30R/W0Must write 0
2DLL PDNR/W0This register applies ONLY to the ADC3543. It powers down the internal DLL, which is used to adjust the sampling time. This register must be enabled when operating at sampling rates below 40 MSPS. When DLL PDN bit is enabled the sampling time is directly dependent on sampling clock duty cycle (with a 50/50 duty the sampling time is TS/2).
0: Sampling time is TS/ 4
1: Sampling time is TS/2 (only for sampling rates below 40 MSPS).
10R/W0Must write 0
0AZ ENR/W0/1This bit enables the internal auto-zero circuitry. It is enabled by default for the ADC3541/42 and disabled for the ADC3543.
0: Auto-zero disabled
1: Auto-zero enabled
Figure 8-59 Register 0x13
76543210
000000E-FUSE LD
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-24 Register 0x13 Field Descriptions
BitFieldTypeResetDescription
7-10R/W0Must write 0
0E-FUSE LDR/W0This register bit loads the internal bit mapping for different interfaces. After setting the interface in register 0x07, this E-FUSE LD bit needs to be set to 1 and reset to 0 for loading to go into effect. Register 0x07 along with the E-Fuse Load (0x13, D0) needs to be loaded first in the programming sequence since the E-Fuse load resets the SPI writes.
0: E-FUSE LOAD set
1: E-FUSE LOAD reset
Figure 8-60 Register 0x14/15/16
76543210
CUSTOM PAT [7:0]
CUSTOM PAT [15:8]

0

0

0

TEST PAT ACUSTOM PAT [17:16]
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-25 Register 0x14, 15, 16 Field Descriptions
BitFieldTypeResetDescription
7-0CUSTOM PAT [17:0]R/W00000000This register is used for two purposes:
  • It sets the constant custom pattern starting from MSB
  • It sets the RAMP pattern increment step size.

00001: Ramp pattern for 18-bit ADC
00100: Ramp pattern for 16-bit ADC
10000: Ramp pattern for 14-bit ADC
7-50R/W0

Must write 0.

4-2TEST PAT AR/W000Enables test pattern output mode for channel A (NOTE: The test pattern is set prior to the bit mapper and is based on native resolution of the ADC starting from the MSB). These work in either output format.
000: Normal output mode (test pattern output disabled)
010: Ramp pattern: need to set proper increment using CUSTOM PAT register
011: Constant Pattern using CUSTOM PAT [17:0] in register 0x14/15/16.
others: not used
Figure 8-61 Register 0x18
76543210
000DCLKIN EN0000
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-26 Register 0x18 Field Descriptions
BitFieldTypeResetDescription
7-50R/W0Must write 0
4DCLKIN ENR/W0This bit enables the DCLKIN clock input buffer for serial CMOS modes. Also DCLKIN EN (0x1F, D6) needs to be set as well.
0: DCLKIN buffer powered down.
1: DCLKIN buffer enabled.
3-00R/W0Must write 0
Figure 8-62 Register 0x19
76543210
FCLK SRC00FCLK DIV00FCLK EN0
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-27 Register 0x19 Field Descriptions
BitFieldTypeResetDescription
7FCLK SRCR/W0User has to select if FCLK signal comes from ADC or from DDC block. Here real decimation is treated same as bypass mode
0: FCLK generated from ADC. FCLK SRC set to 0 for DDC bypass and real decimation mode
1: FCLK generated from DDC block. In complex decimation mode only this bit needs to be set for 2-w and 1-w output interface mode.
6-50R/W0Must write 0
4FCLK DIVR/W0This bit needs to be set to 1 for 2-w output mode in bypass mode only (non decimation).
0: All output interface modes except 2-w bypass mode..
1: 2-w output interface mode.
3-20R/W0Must write 0
1FCLK ENR/W0This bit enables FCLK output for CMOS output.
0: Data output pin is used for parallel output data.
1: Data output pin is used for FCLK output in serialized CMOS mode.
00R/W0

Must write 0

Table 8-28 Configuration of FCLK SRC and FCLK DIV Register Bits vs Serial Interface
BYPASS/DECIMATIONSERIAL INTERFACEFCLK SRCFCLK DIV
Decimation Bypass/ Real Decimation2-wire01
1-wire00
Complex Decimation2-wire10
1-wire10
Figure 8-63 Register 0x1B
76543210
MAPPER EN20B ENBIT MAPPER RES000
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-29 Register 0x1B Field Descriptions
BitFieldTypeResetDescription
7MAPPER ENR/W0This bit enables changing the resolution of the output (including output serialization factor) in bypass mode only.
0: Output bit mapper disabled.
1: Output bit mapper enabled.
620B ENR/W0This bit enables 20-bit output resolution which can be useful for high decimation settings so that quantization noise doesn't impact the ADC performance.
0: 20-bit output resolution disabled.
1: 20-bit output resolution enabled.
5-3BIT MAPPER RESR/W000Sets the output resolution using the bit mapper. MAPPER EN bit (D6) needs to be enabled when operating in bypass mode..
000: 18 bit
001: 16 bit
010: 14 bit
all others, n/a
2-00R/W0Must write 0
Table 8-30 Register Settings for Output Bit Mapper vs Operating Mode
BYPASS/DECIMATIONOUTPUT RESOLUTIONMAPPER EN (D7)BIT MAPPER RES (D5-D3)
Decimation BypassResolution Change1000: 18-bit
001: 16-bit
010: 14-bit
Real DecimationResolution Change (default 18-bit)0
Complex Decimation0
Figure 8-64 Register 0x1E
76543210
00CMOS DCLK DEL0000
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-31 Register 0x1E Field Descriptions
BitFieldTypeResetDescription
7-60R/W0Must write 0
5-4CMOS DCLK DELR/W00These bits adjust the output timing of CMOS DCLK output.
00: no delay
01: DCLK advanced by 50 ps
10: DCLK delayed by 50 ps
11: DCLK delayed by 100 ps
3-00R/W0Must write 0
Figure 8-65 Register 0x1F
76543210
LOW DR ENDCLKIN EN0DCLK OB EN2X DCLK000
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-32 Register 0x1F Field Descriptions
BitFieldTypeResetDescription
7LOW DR ENR/W0This bit impacts the output drive strength of the CMOS output buffers. This bit can be enabled at slow speeds in order to save power consumption but it will also degrade the rise and fall times.
0: Low drive strength disabled.
1: Low drive strength enabled.
6DCLKIN ENR/W0This bit enables the DCLKIN clock input buffer for serial CMOS modes. Also DCLKIN EN (0x18, D4) needs to be set as well.
0: DCLKIN buffer powered down.
1: DCLKIN buffer enabled.
50R/W0Must write 0
4DCLK OB ENR/W1This bit enables DCLK output buffer.
0: DCLK output buffer powered down.
1: DCLK output buffer enabled.
32X DCLKR/W0This bit enables SDR output clocking with serial CMOS mode. When this mode is enabled, DCLKIN required is twice as fast and data is output only on rising edge of DCLK.
0: Normal operation with data output on DCLK rising and falling edge.
1: 2x DCLK mode enabled with data output on DCLK rising edge only.
2-00R/W0Must write 0
Figure 8-66 Register 0x20/21/22
76543210
FCLK PAT [7:0]
FCLK PAT [15:8]
0000FCLK PAT [19:16]
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-33 Register 0x20, 21, 22 Field Descriptions
BitFieldTypeResetDescription
7-0FCLK PAT [19:0]R/W0xFFC00These bits can adjust the duty cycle of the FCLK. In decimation bypass mode the FCLK pattern gets adjusted automatically for the different output resolutions. Table 8-34 shows the proper FCLK pattern values for 1-wire in real/complex decimation.
Table 8-34 FCLK Pattern for different resolution based on interface
DECIMATIONOUTPUT RESOLUTION2-WIRE1-WIRE
REAL DECIMATION14-bitUse Default0xFE000
16-bit0xFF000
18-bit0xFF800
COMPLEX DECIMATION14-bit0xFFFFF
16-bit0xFFFFF
18-bit0xFFFFF
Figure 8-67 Register 0x24
76543210
00000DIG BYPDDC EN0
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-35 Register 0x24 Field Descriptions
BitFieldTypeResetDescription
7-30R/W0Must write 0
2DIG BYPR/W0This bit needs to be set to enable digital features block which includes decimation.
0: Digital feature block bypassed - lowest latency
1: Data path includes digital features
1DDC ENR/W0Enables internal decimation filter
0: DDC disabled.
1: DDC enabled.
00R/W0Must write 0
Figure 8-68 Register control for digital features
Figure 8-69 Register 0x25
76543210
0DECIMATIONREAL OUT00MIX PHASE
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-36 Register 0x25 Field Descriptions
BitFieldTypeResetDescription
70R/W0Must write 0
6-4DECIMATIONR/W000Complex decimation setting.
000: Bypass mode (no decimation)
001: Decimation by 2
010: Decimation by 4
011: Decimation by 8
100: Decimation by 16
101: Decimation by 32
others: not used
3REAL OUTR/W0This bit selects real output decimation. In this mode, the decimation filter is a low pass filter and no complex mixing is performed to reduce power consumption. For maximum power savings the NCO in this case should be set to 0.
0: Complex decimation
1: Real decimation
2-10R/W0Must write 0
0MIX PHASER/W0This bit used to invert the NCO phase
0: NCO phase as is.
1: NCO phase inverted.
Figure 8-70 Register 0x26
76543210
MIX GAIN AMIX RES AFS/4 MIX A0000
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-37 Register 0x26 Field Descriptions
BitFieldTypeResetDescription
7-6MIX GAIN AR/W00This bit applies a 0, 3 or 6-dB digital gain to the output of digital mixer to compensate for the mixing loss for channel A.
00: no digital gain added
01: 3-dB digital gain added
10: 6-dB digital gain added
11: not used
5MIX RES AR/W0Toggling this bit resets the NCO phase of channel A and loads the new NCO frequency. This bit does not self reset.
4FS/4 MIX AR/W0Enables FS/4 mixing for DDC A (complex decimation only).
0: FS/4 mixing disabled.
1: FS/4 mixing enabled.

3-0

0

R/W

0

Must write 0

Figure 8-71 Register 0x27
76543210
000OP ORDER AQ-DEL AFS/4 MIX PH A00
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-38 Register 0x27 Field Descriptions
BitFieldTypeResetDescription
7-50R/W0Must write 0
4OP ORDER AR/W0Swaps the I and Q output order for channel A
0: Output order is I[n], Q[n]
1: Output order is swapped: Q[n], I[n]
3Q-DEL AR/W0This delays the Q-sample output of channel A by one.
0: Output order is I[n], Q[n]
1: Q-sample is delayed by 1 sample: I[n], Q[n+1], I[n+1], Q[n+2]
2FS/4 MIX PH AR/W0Inverts the mixer phase for channel A when using FS/4 mixer
0: Mixer phase is non-inverted
1: Mixer phase is inverted
1-00R/W0Must write 0
Figure 8-72 Register 0x2A/2B/2C/2D
76543210
NCO A [7:0]
NCO A [15:8]
NCO A [23:16]
NCO A [31:24]
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-39 Register 0x2A/2B/2C/2D Field Descriptions
BitFieldTypeResetDescription
7-0NCO A [31:0]R/W0Sets the 32 bit NCO value for decimation filter channel A. The NCO value is fNCO× 232/FS
In real decimation these registers are automatically set to 0.
Figure 8-73 Register 0x39...0x72
76543210
OUTPUT BIT MAPPER
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-40 Register 0x39...0x72 Field Descriptions
BitFieldTypeResetDescription
7-0OUTPUT BIT MAPPERR/W0These registers are used to reorder the output data bus. See the Section 8.3.5.5 on how to program it.
Figure 8-74 Register 0x8F
76543210
000000FORMAT A0
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
Table 8-41 Register 0x8F Field Descriptions
BitFieldTypeResetDescription
7-20R/W0Must write 0
1FORMAT AR/W0This bit sets the output data format for channel A. Digital bypass register bit (0x24, D2) needs to be enabled as well.
0: 2s complement
1: Offset binary
00R/W0Must write 0
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |