ZHCSLJ1C July   2020  – December 2022 ADC3541 , ADC3542 , ADC3543

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications ADC3541
    8. 6.8  Electrical Characteristics - AC Specifications ADC3542
    9. 6.9  Electrical Characteristics - AC Specifications ADC3543
    10. 6.10 Timing Requirements
    11. 6.11 Typical Characteristics: ADC3541
    12. 6.12 Typical Characteristics: ADC3542
    13. 6.13 Typical Characteristics: ADC3543
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Single Ended Input
          3. 8.3.1.2.3 Analog Input Termination and DC Bias
            1. 8.3.1.2.3.1 AC-Coupling
            2. 8.3.1.2.3.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 Digital Filter Operation
        2. 8.3.4.2 FS/4 Mixing with Real Output
        3. 8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
        4. 8.3.4.4 Decimation Filter
        5. 8.3.4.5 SYNC
        6. 8.3.4.6 Output Formatting with Decimation
          1. 8.3.4.6.1 Parallel CMOS
          2. 8.3.4.6.2 Serialized CMOS Interface
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Parallel CMOS Output
        2. 8.3.5.2 Serialized CMOS output
          1. 8.3.5.2.1 SDR Output Clocking
        3. 8.3.5.3 Output Data Format
        4. 8.3.5.4 Output Formatter
        5. 8.3.5.5 Output Bit Mapper
        6. 8.3.5.6 Output Interface/Mode Configuration
          1. 8.3.5.6.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration Using the SPI Interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Map
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Signal Path
        2. 9.2.2.2 Sampling Clock
        3. 9.2.2.3 Voltage Reference
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Set Up
      1. 9.3.1 Register Initialization During Operation
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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6.9 Electrical Characteristics - AC Specifications ADC3543

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 105°C, ADC sampling rate = 65 MSPS, external reference, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, external 1.6V reference, 5 pF output load, and –1-dBFS differential input, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC3543: 65 MSPS
NSD Noise Spectral Density fIN = 1.1 MHz, AIN = -20 dBFS -154.7 dBFS/Hz
SNR Signal to noise ratio fIN = 1.1 MHz 79.0 dBFS
fIN = 5 MHz 77.0 79.0
fIN = 10 MHz 79.0
fIN = 20 MHz 79.0
fIN = 40 MHz 78.5
fIN = 64 MHz 78.0
SINAD Signal to noise and distortion ratio fIN = 1.1 MHz 79.0 dBFS
fIN = 5 MHz 76.0 79.0
fIN = 10 MHz 79.0
fIN = 20 MHz 79.0
fIN = 40 MHz 78.5
fIN = 64 MHz 78.0
ENOB Effective number of bits fIN = 1.1 MHz 12.8 bit
fIN = 5 MHz 12.0 12.8
fIN = 10 MHz 12.8
fIN = 20 MHz 12.8
fIN = 40 MHz 12.5
fIN = 64 MHz 12.0
THD Total Harmonic Distortion (First five harmonics) fIN = 1.1 MHz 92 dBc
fIN = 5 MHz 78 89
fIN = 10 MHz 84
fIN = 20 MHz 86
fIN = 40 MHz 82
fIN = 64 MHz 78
SFDR Spur free dynamic range including second and third harmonic distortion fIN = 1.1 MHz 95 dBc
fIN = 5 MHz 82 90
fIN = 10 MHz 87
fIN = 20 MHz 88
fIN = 40 MHz 85
fIN = 64 MHz 80
Non HD2,3 Spur free dynamic range (excluding HD2 and HD3) fIN = 1.1 MHz 100 dBFS
fIN = 5 MHz 93 101
fIN = 10 MHz 99
fIN = 20 MHz 97
fIN = 40 MHz 96
fIN = 64 MHz 91
IMD3 Two tone inter-modulation distortion f1 = 10 MHz, f2 = 12 MHz, AIN = -7 dBFS/tone 92 dBc
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