ZHCSRD5 December   2022 ADC3544

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Power Consumption
    6. 6.6 Electrical Characteristics - DC Specifications
    7. 6.7 Electrical Characteristics - AC Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Single Ended Input
          3. 8.3.1.2.3 Analog Input Termination and DC Bias
            1. 8.3.1.2.3.1 AC-Coupling
            2. 8.3.1.2.3.2 DC-Coupling
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 Digital Filter Operation
        2. 8.3.4.2 FS/4 Mixing with Real Output
        3. 8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
        4. 8.3.4.4 Decimation Filter
        5. 8.3.4.5 SYNC
        6. 8.3.4.6 Output Formatting with Decimation
          1. 8.3.4.6.1 Parallel CMOS
          2. 8.3.4.6.2 Serialized CMOS Interface
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Parallel CMOS Output
        2. 8.3.5.2 Serialized CMOS output
          1. 8.3.5.2.1 SDR Output Clocking
        3. 8.3.5.3 Output Data Format
        4. 8.3.5.4 Output Formatter
        5. 8.3.5.5 Output Bit Mapper
        6. 8.3.5.6 Output Interface/Mode Configuration
          1. 8.3.5.6.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Signal Path
        2. 9.2.2.2 Sampling Clock
        3. 9.2.2.3 Voltage Reference
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Set Up
      1. 9.3.1 Register Initialization During Operation
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Trademarks
    3. 10.3 Electrostatic Discharge Caution
    4. 10.4 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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8.3.5.6 Output Interface/Mode Configuration

The following sequence summarizes all the relevant registers for changing the output interface and/or enabling the decimation filter. Steps 1 and 2 must come first since the E-Fuse load reset the SPI writes, the remaining steps can come in any order.

Table 8-10 Configuration steps for changing interface or decimation
STEPFEATUREADDRESSDESCRIPTION
1Output Interface0x07Select the output interface bit mapping depending on resolution and output interface.
Output ResolutionSDRDDR2-wire1-wire
14-bit0xC80xA90x2B0x6C
16-bit0x4B
18-bitN/AN/A0x2B
20-bitN/AN/A0x4B
20x13Load the output interface bit mapping using the E-fuse loader (0x13, D0). Program register 0x13 to 0x01, wait ~ 1ms so that bit mapping is loaded properly followed by 0x13 0x00
30x0A/B/CPower down relevant CMOS output buffers to avoid contention.
40x18For serial CMOS modes, DCLKIN EN (D4) needs to be enabled.
50x19When using serial CMOS, configure the FCLK frequency based on bypass/decimation and number of lanes used.
Bypass/DecSCMOSFCLK SRC
(D7)		FCLK DIV
(D4)
Bypass/ Real Decimation2-wire01
1-wire00
1/2-wire00
Complex Decimation2-wire10
1-wire10
1/2-wire00
60x1BSelect the output interface resolution using the bit mapper (D5-D3).
70x1FFor serial CMOS modes, DCLKIN EN (D6) and DCLK OB EN (D4) need to be enabled.
80x20
0x21
0x22		When using serial CMOS, select the FCLK pattern for decimation for proper duty cycle output of the frame clock.
DecimationOutput Resolution2-wire1-wire
Real Decimation14-bituse default0xFE000
16-bit0xFF000
18-bit0xFF800
20-bit0xFFC00
Complex Decimation14-bit0xFFFFF
16-bit
18-bit
20-bit
9 0x39..0x60 Change output bit mapping if desired. This works also with the default interface selection.
10Decimation Filter0x24Enable the decimation filter
110x25Configure the decimation filter
120x2A/B/C/D
Program the NCO frequency for complex decimation (can be skipped for real decimation)
130x27
Configure the complex output data stream (set both bits to 0 for real decimation)
Serial CMOSOP-Order (D4)Q-Delay (D3)
2-wire10
1-wire01
1/2-wire11
140x26Set the mixer gain and toggle the mixer reset bit to update the NCO frequency.
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