There are several critical signals which require specific care during board design:
- Analog input and clock signals
- Traces should be as short as possible and vias should be avoided where possible to minimize impedance discontinuities.
- Traces should be routed using loosely coupled 100-Ω differential traces.
- Differential trace lengths should be matched as close as possible to minimize phase imbalance and HD2 degradation.
- Digital output interface
- A 20 Ω series isolation resistor should be used on each CMOS output and placed
close the digital output. This isolation resistor limits the output
current into the capacitive load and thus minimizes the switching noise
inside the ADC. When driving longer distances a buffer should be used.
The resistor value should be optimized for the desired output data
rate.
- Voltage reference
- The bypass capacitor should be placed as close to the device pins as possible and connected between VREF and REFGND – on top layer avoiding vias.
- Depending on configuration an additional bypass capacitor between REFBUF and REFGND may be recommended and should also be placed as close to pins as possible on top layer.
- Power and ground connections
- Provide low resistance connection paths to all power and ground pins.
- Use power and ground planes instead of traces.
- Avoid narrow, isolated paths which increase the connection resistance.
- Use a signal/ground/power circuit board stackup to maximize coupling between the ground and power plane.