ZHCSMB7A October   2020  – May 2022 ADC3641 , ADC3642 , ADC3643

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications ADC3641
    8. 6.8  Electrical Characteristics - AC Specifications ADC3642
    9. 6.9  Electrical Characteristics - AC Specifications ADC3643
    10. 6.10 Timing Requirements
    11. 6.11 Typical Characteristics - ADC3641
    12. 6.12 Typical Characteristics - ADC3642
    13. 6.13 Typical Characteristics - ADC3643
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Single Ended Input
          3. 8.3.1.2.3 Analog Input Termination and DC Bias
            1. 8.3.1.2.3.1 AC-Coupling
            2. 8.3.1.2.3.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
          1. 8.3.4.2.1 FS/4 Mixing with Real Output
        3. 8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
        4. 8.3.4.4 Decimation Filter
        5. 8.3.4.5 SYNC
        6. 8.3.4.6 Output Formatting with Decimation
          1. 8.3.4.6.1 Parallel CMOS
          2. 8.3.4.6.2 Serialized CMOS
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Parallel CMOS Output
        2. 8.3.5.2 Serialized CMOS output
          1. 8.3.5.2.1 SDR Output Clocking
        3. 8.3.5.3 Output Data Format
        4. 8.3.5.4 Output Formatter
        5. 8.3.5.5 Output Bit Mapper
        6. 8.3.5.6 Output Interface/Mode Configuration
          1. 8.3.5.6.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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6.10 Timing Requirements

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
ADC Timing Specifications
tAD Aperture delay 0.85 ns
tA Aperture jitter Square wave clock with fast edges 180 fs
tJ Jitter on DCLKIN Serial CMOS output mode ± 50 ps (pk-pk)
Recory time from +6 dB overload condition SNR within 1 dB of expected value 1 Clock cycle
tACQ Signal acquisition period, referenced to sampling clock falling edge FS = 10 Msps -TS/2 Sampling Clock Period
FS = 25 Msps -TS/2
FS = 65 Msps -TS/4
tCONV Signal conversion period, referenced to sampling clock falling edge FS = 10 Msps +TS × 1/5 Sampling Clock Period
FS = 25 Msps +TS × 3/8
FS = 65 Msps +TS × 5/8
Wake up time Time to valid data after coming out of power down. Internal reference. Bandgap reference enabled, single ended clock 14.6 us
Bandgap reference enabled, differential clock 14
Bandgap reference disabled, single ended clock 1.6 ms
Bandgap reference disabled, differential clock 1.6
Time to valid data after coming out of power down. External  1.6V reference. Bandgap reference enabled, single ended clock 14.6 us
Bandgap reference enabled, differential clock 14
Bandgap reference disabled, single ended clock 1.13 ms
Bandgap reference disabled, differential clock 1.13
tS,SYNC Setup time for SYNC input signal Referenced to sampling clock rising edge 500 ps
tH,SYNC Hold time for SYNC input signal 600
ADC Latency Signal input to data output DDR CMOS 1 Clock cycles
Serialized CMOS: 2-wire 2
Serialized CMOS: 1-wire 1
Serialized CMOS: 1/2-wire 1
Add. Latency Real decimation by 2 21   Output clock cycles
Complex decimation by 2     22  
Real or complex decimation by 4, 8, 16, 32     23  
INTERFACE TIMING - PARALLEL DDR CMOS
tPD Propagation delay: sampling clock falling edge to DCLK rising edge 3 5 7 ns
tCD DCLK rising edge to output data delay Fout = 10 MSPS -0.70 -0.32 ns
Fout = 25 MSPS -0.66 -0.30
Fout = 65 MSPS -0.73 -0.31
tDV Data valid, DDR CMOS Fout = 10 MSPS 49.35 49.93 ns
Fout = 25 MSPS 19.66 19.77
Fout = 65 MSPS 7.42 7.51
INTERFACE TIMING - SERIAL CMOS
tPD Propagation delay: sampling clock falling edge to DCLK rising edge Delay between sampling clock falling edge to DCLKIN falling edge < 2.5ns.
TDCLK = DCLK period
tCDCLK = Sampling clock falling edge to DCLKIN falling edge		 2 + TDCLK + tCDCLK 3 + TDCLK + tCDCLK 4 + TDCLK + tCDCLK ns
Delay between sampling clock falling edge to DCLKIN falling edge >= 2.5ns.
TDCLK = DCLK period
tCDCLK = Sampling clock falling edge to DCLKIN falling edge		 2 + tCDCLK 3 + tCDCLK 4 + tCDCLK
tCD DCLK rising edge to output data delay,
2-wire serial CMOS		 Fout = 10 MSPS, DA/B5,6 = 80 MBPS -0.24 0.10 ns
Fout = 20 MSPS, DA/B5,6 = 160 MBPS -0.29 0.10
Fout = 30 MSPS, DA/B5,6 = 240 MBPS -0.28 0.09
DCLK rising edge to output data delay,
1-wire series CMOS		 Fout = 5 MSPS, DA/B6 = 80 MBPS -0.22 0.11
Fout = 10 MSPS, DA/B6 = 160 MBPS -0.27 0.11
Fout = 15 MSPS, DA/B6 = 240 MBPS -0.52 0.08
DCLK rising edge to output data delay, 1/2-wire serial CMOS Fout = 5 MSPS, DA6 = 160 MBPS  -0.24 0.10
tDV Data valid, 2-wire serial CMOS Fout = 10 MSPS, DA/B5,6 = 80 MBPS 12.19 12.36 ns
Fout = 20 MSPS, DA/B5,6 = 160 MBPS 5.93 6.1
Fout = 30 MSPS, DA/B5,6 = 240 MBPS 3.91 4.07
Data valid, 1-wire serial CMOS Fout = 5 MSPS, DA/B6 = 80 MBPS 12.21 12.39
Fout = 10 MSPS, DA/B6 = 160 MBPS 5.95 6.1
Fout = 15 MSPS, DA/B6 = 240 MBPS 3.83 4.08
Data valid, 1/2-wire serial CMOS Fout = 5 MSPS, DA6 = 160 MBPS  5.36 6.13
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input
fCLK(SCLK) Serial clock frequency 20 MHz
tSU(SEN) SEN to rising edge of SCLK 10 ns
tH(SEN) SEN from rising edge of SCLK 9
tSU(SDIO) SDIO to rising edge of SCLK 17
tH(SDIO) SDIO from rising edge of SCLK 9
SERIAL PROGRAMMING INTERFACE (SDIO) - Output
t(OZD) SDIO tri-state to driven 3.9 10.8 ns
t(ODZ) SDIO data to tri-state 3.4 14
t(OD) SDIO valid from falling edge of SCLK 3.9 10.8
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