ZHCSQN6 May   2022 ADC3644

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Power Consumption
    6. 6.6 Electrical Characteristics - DC Specifications
    7. 6.7 Electrical Characteristics - AC Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Single Ended Input
          3. 8.3.1.2.3 Analog Input Termination and DC Bias
            1. 8.3.1.2.3.1 AC-Coupling
            2. 8.3.1.2.3.2 DC-Coupling
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Clock Amplitude
        2. 8.3.2.2 Single Ended vs Differential Clock Input
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
        3. 8.3.4.3 FS/4 Mixing with Real Output
        4. 8.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 8.3.4.5 Decimation Filter
        6. 8.3.4.6 SYNC
        7. 8.3.4.7 Output Formatting with Decimation
          1. 8.3.4.7.1 Parallel CMOS
          2. 8.3.4.7.2 Serialized CMOS Interface
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Parallel CMOS Output
        2. 8.3.5.2 Serialized CMOS output
          1. 8.3.5.2.1 SDR Output Clocking
        3. 8.3.5.3 Output Data Format
        4. 8.3.5.4 Output Formatter
        5. 8.3.5.5 Output Bit Mapper
        6. 8.3.5.6 Output Interface or Mode Configuration
          1. 8.3.5.6.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support (Optional)
      1. 10.1.1 Development Support (Optional)
      2. 10.1.2 Device Nomenclature (Optional)
    2. 10.2 Documentation Support (if applicable)
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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8.3.5.5 Output Bit Mapper

The output bit mapper allows to change the output bit order for any selected interface mode.

Figure 8-36 Output Bit Mapper

It is a two step process to change the output bit mapping and assemble the output data bus:

  1. Both channel A and B can have up to 20-bit output. Each output bit of either channel has a unique identifier bit as shown in the Table 8-8. The MSB starts with bit D19 – depending on output resolution chosen the LSB would be D6 (14-bit) to D0 (20-bit). The ‘previous sample’ is only needed in 2-w mode.
  2. The bit mapper is then used to assemble the output sample. The following sections detail how to remap both a parallel and a serial output format.

Table 8-8 Unique identifier of each data bit
BitChannel AChannel B
Previous sample (2-w only)Current samplePrevious sample (2-w only)Current sample
D19 (MSB)0x2D0x6D0x290x69
D180x2C0x6C0x280x68
D170x270x670x230x63
D160x260x660x220x62
D150x250x650x210x61
D140x240x640x200x60
D130x1F0x5F0x1B0x5B
D120x1E0x5E0x1A0x5A
D110x1D0x5D0x190x59
D100x1C0x5C0x180x58
D90x170x570x130x53
D80x160x560x120x52
D70x150x550x110x51
D60x140x540x100x50
D50x0F0x4F0x0B0x4B
D40x0E0x4E0x0A0x4A
D30x0D0x4D0x090x49
D20x0C0x4C0x080x48
D10x070x470x030x43
D0 (LSB)0x060x460x020x42

In parallel DDR mode, a data bit (with unique identifier) needs to be assigned to each output pin for both the rising and the falling edge of the DCLK using the register addresses as shown in Figure 8-37. The example on the right shows the output data bus remapped to where all 14 bit of channel A is output on DCLK rising edge followed by all 14 bit of channel B on DCLK falling edge.

Figure 8-37 DDR output timing diagram with output mapping (left) and example (right)

In the serial output mode, a data bit (with unique identifier) needs to be assigned to each location within the serial output stream. There are a total of 40 addresses available per channel. Channel A spans from address 0x39 to 0x60 and channel B from address 0x61 to 0x88. When using complex decimation, the output bit mapper is applied to both the “I” and the “Q” sample.

2-wire mode: in this mode both the current and the previous sample have to be used in the address space as shown in Figure 8-38 below. The address order is different for 14/18-bit and 16/20-bit. Note: there are unused addresses between samples for resolution less than 20-bit (grey back ground), which can be skipped if not used.

Figure 8-38 2-wire output bit mapper

In the following example (Figure 8-39), the 16-bit 2-wire serial output is reordered to where lane DA5/DB5 carries the 8 MSB and lane DA6/DB6 carries 8 LSBs.

Figure 8-39 Example: 2-wire output mapping

1-wire mode: Only the ‘current’ sample needs to programmed in the address space. If desired, it can be duplicated on DA5/DB5 as well (using addresses shown below) in order to have a redundant output. Lane DA5/DB5 needs to be powered up in that case.

Figure 8-40 1-wire output bit mapping

½-wire mode: The output is only on lane DA6 and the sample order is programmed into the 40 addresses of chA (from 0x39 to 0x60). It covers 2 samples (one for chA, one for chB) as shown below.

Figure 8-41 1/2-wire output bit mapping
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