ZHCSQN6 May   2022 ADC3644

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Power Consumption
    6. 6.6 Electrical Characteristics - DC Specifications
    7. 6.7 Electrical Characteristics - AC Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Single Ended Input
          3. 8.3.1.2.3 Analog Input Termination and DC Bias
            1. 8.3.1.2.3.1 AC-Coupling
            2. 8.3.1.2.3.2 DC-Coupling
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Clock Amplitude
        2. 8.3.2.2 Single Ended vs Differential Clock Input
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
        3. 8.3.4.3 FS/4 Mixing with Real Output
        4. 8.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 8.3.4.5 Decimation Filter
        6. 8.3.4.6 SYNC
        7. 8.3.4.7 Output Formatting with Decimation
          1. 8.3.4.7.1 Parallel CMOS
          2. 8.3.4.7.2 Serialized CMOS Interface
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Parallel CMOS Output
        2. 8.3.5.2 Serialized CMOS output
          1. 8.3.5.2.1 SDR Output Clocking
        3. 8.3.5.3 Output Data Format
        4. 8.3.5.4 Output Formatter
        5. 8.3.5.5 Output Bit Mapper
        6. 8.3.5.6 Output Interface or Mode Configuration
          1. 8.3.5.6.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support (Optional)
      1. 10.1.1 Development Support (Optional)
      2. 10.1.2 Device Nomenclature (Optional)
    2. 10.2 Documentation Support (if applicable)
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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8.3.5.4 Output Formatter

The digital output interface uses a flexible output formatter Figure 8-35. The output formatter takes the 14-bit output directly from the ADC or from digital filter block and reformats it to a resolution of 14, 16, 18 or 20-bit. With parallel output format the maximum output resolution supported is 14-bit. With serial CMOS output the output serialization factor gets adjusted accordingly for 2-, 1- and 1/2-wire interface mode. The maximum output data rate can not be exceeded independently of output resolution and serialization factor.

Figure 8-35 Interface output bit formatter

Table 8-7 provides an overview for the resulting serialization factor depending on output resolution and output modes. Note that the DCLKIN frequency needs to be adjusted accordingly as well. Changing the output resolution to 16-bit, 2-wire mode for example would result in DCLKIN = FS * 4 instead of * 3.5.

The output bit formatter can be used for DDC bypass and decimation filter.

Table 8-7 Serialization factor vs output resolution for different output modes
OUTPUT RESOLUTION Interface SERIALIZATION FCLK DCLKIN DCLK D0/D1
14-bit (default) 2-Wire 7x FS/2 FS* 3.5 FS* 3.5 FS* 7
1-Wire 14x FS FS* 7 FS* 7 FS* 14
½-Wire 28x FS FS* 14 FS* 14 FS* 28
16-bit 2-Wire 8x FS/2 FS* 4 FS* 4 FS* 8
1-Wire 16x FS FS* 8 FS* 8 FS* 16
½-Wire 32x FS FS* 16 FS* 16 FS* 32
18-bit 2-Wire 9x FS/2 FS* 4.5 FS* 4.5 FS* 9
1-Wire 18x FS FS* 9 FS* 9 FS* 18
½-Wire 36x FS FS* 18 FS* 18 FS* 36
20-bit 2-Wire 10x FS/2 FS* 5 FS* 5 FS* 10
1-Wire 20x FS FS* 10 FS* 10 FS* 20
½-Wire 40x FS FS* 20 FS* 20 FS* 40

The programming sequence to change the output interface and/or resolution from default settings is shown in Output Interface or Mode Configuration.
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