ZHCSQN6 May   2022 ADC3644

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Power Consumption
    6. 6.6 Electrical Characteristics - DC Specifications
    7. 6.7 Electrical Characteristics - AC Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Single Ended Input
          3. 8.3.1.2.3 Analog Input Termination and DC Bias
            1. 8.3.1.2.3.1 AC-Coupling
            2. 8.3.1.2.3.2 DC-Coupling
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Clock Amplitude
        2. 8.3.2.2 Single Ended vs Differential Clock Input
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
        3. 8.3.4.3 FS/4 Mixing with Real Output
        4. 8.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 8.3.4.5 Decimation Filter
        6. 8.3.4.6 SYNC
        7. 8.3.4.7 Output Formatting with Decimation
          1. 8.3.4.7.1 Parallel CMOS
          2. 8.3.4.7.2 Serialized CMOS Interface
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Parallel CMOS Output
        2. 8.3.5.2 Serialized CMOS output
          1. 8.3.5.2.1 SDR Output Clocking
        3. 8.3.5.3 Output Data Format
        4. 8.3.5.4 Output Formatter
        5. 8.3.5.5 Output Bit Mapper
        6. 8.3.5.6 Output Interface or Mode Configuration
          1. 8.3.5.6.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support (Optional)
      1. 10.1.1 Development Support (Optional)
      2. 10.1.2 Device Nomenclature (Optional)
    2. 10.2 Documentation Support (if applicable)
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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6.9 Typical Characteristics

Typical values at TA = 25 °C, ADC sampling rate = 125 MSPS, AIN = –1 dBFS differential input, AVDD = IOVDD = 1.8 V, 1.6 V external reference, 5 pF load capacitance, unless otherwise noted.

AIN = - 1 dBFS, SNR = 75 dBFS
Figure 6-1 Single Tone FFT at FIN = 5 MHz
AIN = - 20 dBFS, SNR = 75.6 dBFS
Figure 6-3 Single Tone FFT at FIN = 10 MHz
AIN = - 1 dBFS, SNR = 72 dBFS
Figure 6-5 Single Tone FFT at FIN = 70 MHz
AIN = - 1 dBFS, SNR = 67 dBFS
Figure 6-7 Single Tone FFT at FIN = 150 MHz
AIN = -20 dBFS, IMD3 = 93 dBc
Figure 6-9 Two Tone FFT at FIN = 10/12 MHz
AIN = -20 dBFS, IMD3 = 84 dBc
Figure 6-11 Two Tone FFT at FIN = 90/92 MHz
Figure 6-13 ENOB vs Input Frequency
GUID-20211028-SS0I-ZWT5-W42P-T4LHLZMBSZP6-low.png
FIN = 5 MHz
Figure 6-15 AC Performance vs Sampling Rate
GUID-20211028-SS0I-BH6G-FCD2-BRGMKTV36QFG-low.png
FIN = 5 MHz
Figure 6-17 AC Performance vs AVDD
GUID-20211028-SS0I-K1MT-DGZB-XJQPVRGKKNLD-low.png
Figure 6-19 Isolations vs Input Frequency
FIN = 5 MHz
Figure 6-21 DNL vs Code
GUID-20211028-SS0I-WT2L-KKZP-FCQ7JZMFTR34-low.png
Pulse Input = 1 MHz
Figure 6-23 Two Tone FFT at FIN = 10/12 MHz
FIN = 1 MHz, 2-w serial CMOS
Figure 6-25 IIOVDD Current vs Decimation
AIN = - 1 dBFS, SNR = 74.7 dBFS
Figure 6-2 Single Tone FFT at FIN = 10 MHz
AIN = - 1 dBFS, SNR = 73 dBFS
Figure 6-4 Single Tone FFT at FIN = 40 MHz
AIN = - 1 dBFS, SNR = 69 dBFS
Figure 6-6 Single Tone FFT at FIN = 100 MHz
AIN = -7 dBFS, IMD3 = 93 dBc
Figure 6-8 Two Tone FFT at FIN = 10/12 MHz
AIN = -7 dBFS, IMD3 = 72 dBc
Figure 6-10 Two Tone FFT at FIN = 90/92 MHz
Figure 6-12 AC Performance vs Input Frequency
FIN = 5 MHz
Figure 6-14 SNR, SFDR vs Input Amplitude
GUID-20211028-SS0I-FVDV-3BMT-SCBBSCBT83QX-low.png
FIN = 5 MHz
Figure 6-16 AC Performance vs Clock Amplitude
FIN = 5 MHz
Figure 6-18 AC Performance vs VCM vs Temperature
FIN = 5 MHz
Figure 6-20 INL vs Code
GUID-20211028-SS0I-6BQD-QQP0-SDRNJBDLP64V-low.png
DC Input = +0.95V
Figure 6-22 DC Offset Histogram
FIN = 1 MHz
Figure 6-24 Current vs Sampling Rate
FIN = 1 MHz, DDR CMOS
Figure 6-26 IIOVDD Current vs Load Capacitance
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