ZHCSM31B September   2020  – March 2022 ADC3660

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Power Consumption
    6. 6.6 Electrical Characteristics - DC Specifications
    7. 6.7 Electrical Characteristics - AC Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Analog Input Termination and DC Bias
            1. 8.3.1.2.2.1 AC-Coupling
            2. 8.3.1.2.2.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
          1. 8.3.4.2.1 FS/4 Mixing with Real Output
        3. 8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
        4. 8.3.4.4 Decimation Filter
        5. 8.3.4.5 SYNC
        6. 8.3.4.6 Output Formatting with Decimation
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 SDR Output Clocking
        2. 8.3.5.2 Output Data Format
        3. 8.3.5.3 Output Formatter
        4. 8.3.5.4 Output Bit Mapper
        5. 8.3.5.5 Output Interface/Mode Configuration
          1. 8.3.5.5.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Power Down Options
      3. 8.4.3 Digital Channel Averaging
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 支持资源
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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6.6 Electrical Characteristics - DC Specifications

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, and –1-dBFS differential input, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC ACCURACY
No missing codes 16 bits
PSRR FIN = 1 MHz 50 dB
DNL Differential nonlinearity FIN = 5 MHz -0.5 ± 0.2 +1 LSB
INL(1) Integral nonlinearity FIN = 5 MHz -4.5 ± 2 +4.5 LSB
VOS_ERR Offset error -130 2 130 LSB
VOS_DRIFT Offset drift over temperature -3.5 LSB/ºC
GAINERR Gain error External 1.6V Reference 0 %FSR
GAINDRIFT Gain drift over temperature External 1.6V Reference 10.3 ppm/ºC
GAINERR Gain error Internal Reference 2.4 %FSR
GAINDRIFT Gain drift over temperature Internal Reference 108.8 ppm/ºC
Transition Noise 1.5 LSB
ADC ANALOG INPUT (AINP/M, BINP/M)
FS Input full scale Differential 3.2 Vpp
VCM Input common model voltage 0.9 0.95 1.0 V
RIN Differential input resistance FIN = 100 kHz 8 kΩ
CIN Differential input Capacitance FIN = 100 kHz 7 pF
VOCM Output common mode voltage 0.95 V
BW Analog Input Bandwidth (-3dB) 900 MHz
INTERNAL VOLTAGE REFERENCE
VREF Internal reference voltage 1.6 V
VREF Output Impedance 8 Ω
REFERENCE INPUT BUFFER (REFBUF)
External reference voltage 1.2 V
EXTERNAL VOLTAGE REFERENCE (VREF)
VREF External voltage reference 1.6 V
Input Current 0.3 mA
Input impedance 5.3 kΩ
CLOCK INPUT (CLKP/M)
Input clock frequency 0.5 65 MHz
VID Differential input voltage 1 3.6 Vpp
VCM Input common mode voltage 0.9 V
RIN Single ended input resistance to common mode. 5 kΩ
CIN Single ended input capacitance 1.5 pF
Clock duty cycle 40 50 60 %
DIGITAL INPUTS (RESET, PDN, SCLK, SEN, SDIO)
VIH High level input voltage 1.4 V
VIL Low level input voltage 0.4 V
IIH High level input current 90 150 uA
IIL Low level input current -150 -90 uA
CI Input capacitance 1.5 pF
DIGITAL OUTPUT (SDOUT)
VOH High level output voltage ILOAD = -400 uA IOVDD – 0.1 IOVDD V
VOL Low level output voltage ILOAD = 400 uA 0.1 V
DIGITAL SCMOS OUTPUTS (DA5/6, DB5/6)
Output data rate per CMOS output pin 250 MHz
VOH High level output voltage IOVDD – 0.1 IOVDD V
VOL Low level output voltage ILOAD = 400 uA 0.1 V
VIH High level input voltage DCLKIN IOVDD – 0.1 IOVDD V
VIL Low level input voltage 0.1 V
(1) Performance data shown is prior to decimation filtering. With DDC enabled, performance improves by the decimation filtering process.
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