ZHCSM31B September   2020  – March 2022 ADC3660

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Power Consumption
    6. 6.6 Electrical Characteristics - DC Specifications
    7. 6.7 Electrical Characteristics - AC Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Analog Input Termination and DC Bias
            1. 8.3.1.2.2.1 AC-Coupling
            2. 8.3.1.2.2.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
          1. 8.3.4.2.1 FS/4 Mixing with Real Output
        3. 8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
        4. 8.3.4.4 Decimation Filter
        5. 8.3.4.5 SYNC
        6. 8.3.4.6 Output Formatting with Decimation
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 SDR Output Clocking
        2. 8.3.5.2 Output Data Format
        3. 8.3.5.3 Output Formatter
        4. 8.3.5.4 Output Bit Mapper
        5. 8.3.5.5 Output Interface/Mode Configuration
          1. 8.3.5.5.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Power Down Options
      3. 8.4.3 Digital Channel Averaging
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 支持资源
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

6.8 Timing Requirements

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, 5 pF output load, and –1-dBFS differential input, unless otherwise noted
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
ADC TIMING SPECIFICATIONS
tAD Aperture Delay 0.85 ns
tA Aperture Jitter square wave clock with fast edges 180 fs
tJ Jitter on DCLKIN ± 50 ps pk-pk 
tACQ Signal acquisition period, Default referenced to sampling clock falling edge -TS/4 Sampling Clock Period
tCONV Signal conversion period referenced to sampling clock falling edge 10 ns
Wake up time Time to valid data after coming out of power down. Internal reference. Bandgap reference enabled, single ended clock 14.6 us
Bandgap reference enabled, differential clock 14.0
Bandgap reference disabled, single ended clock 1.7 ms
Bandgap reference disabled, differential clock 2.1
Time to valid data after coming out of power down. External  1.6V reference. Bandgap reference enabled, single ended clock 14.6 us
Bandgap reference enabled, differential clock 14.0
Bandgap reference disabled, single ended clock 1.8 ms
Bandgap reference disabled, differential clock 1.7
tS,SYNC Setup time for SYNC input signal Referenced to sampling clock rising edge 500 ps
tH,SYNC Hold time for SYNC input signal 600
ADC Latency  Signal input to data output Serialized CMOS: 2-wire 2 ADC clock cycles
Serialized CMOS: 1-wire 1
Serialized CMOS: 1/2-wire 1
Add. Latency Real decimation by 2 21   Output clock cycles
Complex decimation by 2   22  
Real or complex decimation by 4, 8, 16, 32     23  
INTERFACE TIMING
tPD Propagation delay: sampling clock falling edge to DCLK rising edge Delay between sampling clock falling edge to DCLKIN falling edge < 2.5ns.
TDCLK = DCLK period
tCDCLK = Sampling clock falling edge to DCLKIN falling edge		 2 + TDCLK + tCDCLK 3 + TDCLK + tCDCLK 4 + TDCLK + tCDCLK ns
Delay between sampling clock falling edge to DCLKIN falling edge >= 2.5ns.
TDCLK = DCLK period
tCDCLK = Sampling clock falling edge to DCLKIN falling edge		 2 + tCDCLK 3 + tCDCLK 4 + tCDCLK
tCD DCLK rising edge to output data delay
2-wire serial CMOS		 Fout = 10 MSPS, DA/B5,6 = 80 MBPS -0.24 0.10 ns
Fout = 20 MSPS, DA/B5,6 = 160 MBPS -0.29 0.10
Fout = 30 MSPS, DA/B5,6 = 240 MBPS -0.28 0.09
DCLK rising edge to output data delay
1-wire serial CMOS		 Fout = 5 MSPS, DA/B6 = 80 MBPS -0.22 0.11
Fout = 10 MSPS, DA/B6 = 160 MBPS -0.27 0.11
Fout = 15 MSPS, DA/B6 = 240 MBPS -0.52 0.08
DCLK rising edge to output data delay
1/2-wire serial CMOS		 Fout = 5 MSPS, DA6 = 160 MBPS  -0.24 0.1
tDV Data valid, 2-wire serial CMOS Fout = 10 MSPS, DA/B5,6 = 80 MBPS 12.19 12.36 ns
Fout = 20 MSPS, DA/B5,6 = 160 MBPS 5.93 6.1
Fout = 30 MSPS, DA/B5,6 = 240 MBPS 3.91 4.07
Data valid, 1-wire serial CMOS Fout = 5 MSPS, DA/B6 = 80 MBPS 12.21 12.39
Fout = 10 MSPS, DA/B6 = 160 MBPS 5.95 6.10
Fout = 15 MSPS, DA/B6 = 240 MBPS 3.83 4.08
Data valid, 1/2-wire serial CMOS Fout = 5 MSPS, DA6 = 160 MBPS  5.36 6.13
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input
fCLK,SCLK Serial clock frequency 20 MHz
tS,SEN SEN falling edge to SCLK rising edge 10 ns
tH,SEN SCLK rising edge to SEN rising edge 9
tS,SDIO SDIO setup time from rising edge of SCLK 17
tH,SDIO SDIO hold time from rising edge of SCLK 9
SERIAL PROGRAMMING INTERFACE (SDIO) - Output
tOZD Delay from falling edge of 16th SCLK cycle during read operation for SDIO transition from tri-state to valid data 3.9 10.8 ns
tODZ Delay from SEN rising edge for SDIO transition from valid data to tri-state 3.4 14
tOD Delay from falling edge of 16th SCLK cycle during read operation to SDIO valid 3.9 10.8
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