ZHCSNC4B February   2021  – September 2022 ADC3661 , ADC3662 , ADC3663

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Timing Requirements
    9. 6.9  Typical Characteristics - ADC3661
    10. 6.10 Typical Characteristics - ADC3662
    11. 6.11 Typical Characteristics - ADC3663
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Analog Input Termination and DC Bias
            1. 8.3.1.2.2.1 AC-Coupling
            2. 8.3.1.2.2.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
        3. 8.3.4.3 FS/4 Mixing with Real Output
        4. 8.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 8.3.4.5 Decimation Filter
        6. 8.3.4.6 SYNC
        7. 8.3.4.7 Output Formatting with Decimation
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Output Formatter
        2. 8.3.5.2 Output Bit Mapper
        3. 8.3.5.3 Output Scrambler
        4. 8.3.5.4 Output Interface/Mode Configuration
          1. 8.3.5.4.1 Configuration Example
        5. 8.3.5.5 Output Data Format
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
      3. 8.4.3 Digital Channel Averaging
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Map
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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订购信息

5 Pin Configuration and Functions

GUID-740BDBC5-96A5-47E7-B63E-CE58B8114D37-low.gifFigure 5-1 RSB (WQFN) Package, 40-Pin
(Top View)
Table 5-1 Pin Descriptions
PINTYPEDescription
NameNo.
INPUT/REFERENCE
AINP12IPositive analog input, channel A
AINM13INegative analog input, channel A
BINP39IPositive analog input, channel B
BINM38INegative analog input, channel B
VCM8OCommon-mode voltage output for the analog inputs, 0.95V
VREF2IExternal voltage reference input, 1.6V
REFBUF4I1.2V external voltage reference input for use with internal reference buffer. Internal 100 kΩ pull-up resistor to AVDD. This pin is also used to configure default operating conditions.
REFGND3IReference ground input, 0V
CLOCK
CLKP6IPositive differential sampling clock input for the ADC
CLKM7INegative differential sampling clock input for the ADC
CONFIGURATION
PDN/SYNC1IPower down/Synchronization input. This pin can be configured via the SPI interface. Active high. This pin has an internal 21 kΩ pull-down resistor.
RESET9IHardware reset. Active high. This pin has an internal 21 kΩ pull-down resistor.
SEN16ISerial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD.
SCLK35ISerial interface clock input. This pin has an internal 21 kΩ pull-down resistor.
SDIO10I/OSerial interface data input and output. This pin has an internal 21 kΩ pull-down resistor.
NC27-Do not connect
DIGITAL INTERFACE
DA0P20OPositive differential serial LVDS output for lane 0, channel A
DA0M19ONegative differential serial LVDS output for lane 0, channel A
DA1P18OPositive differential serial LVDS output for lane 1, channel A
DA1M17ONegative differential serial LVDS output for lane 1, channel A
DB0P31OPositive differential serial LVDS output for lane 0, channel B
DB0M32ONegative differential serial LVDS output for lane 0, channel B
DB1P33OPositive differential serial LVDS output for lane 1, channel B
DB1M34ONegative differential serial LVDS output for lane 1, channel B
DCLKP23OPositive differential serial LVDS bit clock output.
DCLKM22ONegative differential serial LVDS bit clock output.
FCLKP28OPositive differential serial LVDS frame clock output.
FCLKM29ONegative differential serial LVDS frame clock output.
DCLKINP25IPositive differential serial LVDS bit clock input. Internal 100 Ω differential termination.
DCLKINM24INegative differential serial LVDS bit clock input. Internal 100 Ω differential termination.
POWER SUPPLY
AVDD5,15,36IAnalog 1.8 V power supply
GND11,14,37,40, PowerPadIGround, 0 V
IOVDD21,30I1.8 V power supply for digital interface
IOGND26IGround, 0 V for digital interface
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